include/configs/T102xQDS.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_BOOKE
  16 #define CONFIG_E500                     /* BOOKE e500 family */
  17 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  18 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  19 #define CONFIG_MP                       /* support multiple processors */
  20 #define CONFIG_ENABLE_36BIT_PHYS
  21
  22 #ifdef CONFIG_PHYS_64BIT
  23 #define CONFIG_ADDR_MAP         1
  24 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  25 #endif
  26
  27 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  28 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  29 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  30
  31 #define CONFIG_ENV_OVERWRITE
  32
  33 #define CONFIG_DEEP_SLEEP
  34 #if defined(CONFIG_DEEP_SLEEP)
  35 #define CONFIG_BOARD_EARLY_INIT_F
  36 #endif
  37
  38 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  39
  40 #ifdef CONFIG_RAMBOOT_PBL
  41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  42 #define CONFIG_SPL_FLUSH_IMAGE
  43 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  44 #define CONFIG_SYS_TEXT_BASE            0x00201000
  45 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  46 #define CONFIG_SPL_PAD_TO               0x40000
  47 #define CONFIG_SPL_MAX_SIZE             0x28000
  48 #define RESET_VECTOR_OFFSET             0x27FFC
  49 #define BOOT_PAGE_OFFSET                0x27000
  50 #ifdef CONFIG_SPL_BUILD
  51 #define CONFIG_SPL_SKIP_RELOCATE
  52 #define CONFIG_SPL_COMMON_INIT_DDR
  53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  54 #define CONFIG_SYS_NO_FLASH
  55 #endif
  56
  57 #ifdef CONFIG_NAND
  58 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  59 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  60 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  61 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  62 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  64 #define CONFIG_SPL_NAND_BOOT
  65 #endif
  66
  67 #ifdef CONFIG_SPIFLASH
  68 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  69 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  74 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  75 #ifndef CONFIG_SPL_BUILD
  76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  77 #endif
  78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  79 #define CONFIG_SPL_SPI_BOOT
  80 #endif
  81
  82 #ifdef CONFIG_SDCARD
  83 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  84 #define CONFIG_SPL_MMC_MINIMAL
  85 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  86 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  87 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  88 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  89 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  90 #ifndef CONFIG_SPL_BUILD
  91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  92 #endif
  93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  94 #define CONFIG_SPL_MMC_BOOT
  95 #endif
  96
  97 #endif /* CONFIG_RAMBOOT_PBL */
  98
  99 #ifndef CONFIG_SYS_TEXT_BASE
 100 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 101 #endif
 102
 103 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 104 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 105 #endif
 106
 107 #ifndef CONFIG_SYS_NO_FLASH
 108 #define CONFIG_FLASH_CFI_DRIVER
 109 #define CONFIG_SYS_FLASH_CFI
 110 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 111 #endif
 112
 113 /* PCIe Boot - Master */
 114 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 115 /*
 116  * for slave u-boot IMAGE instored in master memory space,
 117  * PHYS must be aligned based on the SIZE
 118  */
 119 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 120 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 121 #ifdef CONFIG_PHYS_64BIT
 122 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 123 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 124 #else
 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 126 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 127 #endif
 128 /*
 129  * for slave UCODE and ENV instored in master memory space,
 130  * PHYS must be aligned based on the SIZE
 131  */
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 134 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 135 #else
 136 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 137 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 138 #endif
 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 140 /* slave core release by master*/
 141 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 142 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 143
 144 /* PCIe Boot - Slave */
 145 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 146 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 147 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 148                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 149 /* Set 1M boot space for PCIe boot */
 150 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 152                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 153 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 154 #define CONFIG_SYS_NO_FLASH
 155 #endif
 156
 157 #if defined(CONFIG_SPIFLASH)
 158 #define CONFIG_SYS_EXTRA_ENV_RELOC
 159 #define CONFIG_ENV_IS_IN_SPI_FLASH
 160 #define CONFIG_ENV_SPI_BUS              0
 161 #define CONFIG_ENV_SPI_CS               0
 162 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 163 #define CONFIG_ENV_SPI_MODE             0
 164 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 165 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 166 #define CONFIG_ENV_SECT_SIZE            0x10000
 167 #elif defined(CONFIG_SDCARD)
 168 #define CONFIG_SYS_EXTRA_ENV_RELOC
 169 #define CONFIG_ENV_IS_IN_MMC
 170 #define CONFIG_SYS_MMC_ENV_DEV          0
 171 #define CONFIG_ENV_SIZE                 0x2000
 172 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 173 #elif defined(CONFIG_NAND)
 174 #define CONFIG_SYS_EXTRA_ENV_RELOC
 175 #define CONFIG_ENV_IS_IN_NAND
 176 #define CONFIG_ENV_SIZE                 0x2000
 177 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 178 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 179 #define CONFIG_ENV_IS_IN_REMOTE
 180 #define CONFIG_ENV_ADDR         0xffe20000
 181 #define CONFIG_ENV_SIZE         0x2000
 182 #elif defined(CONFIG_ENV_IS_NOWHERE)
 183 #define CONFIG_ENV_SIZE         0x2000
 184 #else
 185 #define CONFIG_ENV_IS_IN_FLASH
 186 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 187 #define CONFIG_ENV_SIZE         0x2000
 188 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 189 #endif
 190
 191 #ifndef __ASSEMBLY__
 192 unsigned long get_board_sys_clk(void);
 193 unsigned long get_board_ddr_clk(void);
 194 #endif
 195
 196 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 197 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 198
 199 /*
 200  * These can be toggled for performance analysis, otherwise use default.
 201  */
 202 #define CONFIG_SYS_CACHE_STASHING
 203 #define CONFIG_BACKSIDE_L2_CACHE
 204 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 205 #define CONFIG_BTB                      /* toggle branch predition */
 206 #define CONFIG_DDR_ECC
 207 #ifdef CONFIG_DDR_ECC
 208 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 209 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 210 #endif
 211
 212 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 213 #define CONFIG_SYS_MEMTEST_END          0x00400000
 214 #define CONFIG_SYS_ALT_MEMTEST
 215 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 216
 217 /*
 218  *  Config the L3 Cache as L3 SRAM
 219  */
 220 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 221 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 222 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 223 #ifdef CONFIG_RAMBOOT_PBL
 224 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 225 #endif
 226 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 227 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 228 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 229 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 230
 231 #ifdef CONFIG_PHYS_64BIT
 232 #define CONFIG_SYS_DCSRBAR              0xf0000000
 233 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 234 #endif
 235
 236 /* EEPROM */
 237 #define CONFIG_ID_EEPROM
 238 #define CONFIG_SYS_I2C_EEPROM_NXID
 239 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 240 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 244
 245 /*
 246  * DDR Setup
 247  */
 248 #define CONFIG_VERY_BIG_RAM
 249 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 250 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 251 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 252 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 253 #define CONFIG_DDR_SPD
 254 #ifndef CONFIG_SYS_FSL_DDR4
 255 #define CONFIG_SYS_FSL_DDR3
 256 #endif
 257
 258 #define CONFIG_SYS_SPD_BUS_NUM  0
 259 #define SPD_EEPROM_ADDRESS      0x51
 260
 261 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 262
 263 /*
 264  * IFC Definitions
 265  */
 266 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 267 #ifdef CONFIG_PHYS_64BIT
 268 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 269 #else
 270 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 271 #endif
 272
 273 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 274 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 275                                 + 0x8000000) | \
 276                                 CSPR_PORT_SIZE_16 | \
 277                                 CSPR_MSEL_NOR | \
 278                                 CSPR_V)
 279 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 280 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 281                                 CSPR_PORT_SIZE_16 | \
 282                                 CSPR_MSEL_NOR | \
 283                                 CSPR_V)
 284 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 285 /* NOR Flash Timing Params */
 286 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 287 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 288                                 FTIM0_NOR_TEADC(0x5) | \
 289                                 FTIM0_NOR_TEAHC(0x5))
 290 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 291                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 292                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 293 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 294                                 FTIM2_NOR_TCH(0x4) | \
 295                                 FTIM2_NOR_TWPH(0x0E) | \
 296                                 FTIM2_NOR_TWP(0x1c))
 297 #define CONFIG_SYS_NOR_FTIM3    0x0
 298
 299 #define CONFIG_SYS_FLASH_QUIET_TEST
 300 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 301
 302 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 303 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 304 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 305 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 306
 307 #define CONFIG_SYS_FLASH_EMPTY_INFO
 308 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 309                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 310 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 311 #define QIXIS_BASE              0xffdf0000
 312 #ifdef CONFIG_PHYS_64BIT
 313 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 314 #else
 315 #define QIXIS_BASE_PHYS         QIXIS_BASE
 316 #endif
 317 #define QIXIS_LBMAP_SWITCH              0x06
 318 #define QIXIS_LBMAP_MASK                0x0f
 319 #define QIXIS_LBMAP_SHIFT               0
 320 #define QIXIS_LBMAP_DFLTBANK            0x00
 321 #define QIXIS_LBMAP_ALTBANK             0x04
 322 #define QIXIS_RST_CTL_RESET             0x31
 323 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 324 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 325 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 326 #define QIXIS_RST_FORCE_MEM             0x01
 327
 328 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 329 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 330                                 | CSPR_PORT_SIZE_8 \
 331                                 | CSPR_MSEL_GPCM \
 332                                 | CSPR_V)
 333 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 334 #define CONFIG_SYS_CSOR3        0x0
 335 /* QIXIS Timing parameters for IFC CS3 */
 336 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 337                                         FTIM0_GPCM_TEADC(0x0e) | \
 338                                         FTIM0_GPCM_TEAHC(0x0e))
 339 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 340                                         FTIM1_GPCM_TRAD(0x3f))
 341 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 342                                         FTIM2_GPCM_TCH(0x8) | \
 343                                         FTIM2_GPCM_TWP(0x1f))
 344 #define CONFIG_SYS_CS3_FTIM3            0x0
 345
 346 #define CONFIG_NAND_FSL_IFC
 347 #define CONFIG_SYS_NAND_BASE            0xff800000
 348 #ifdef CONFIG_PHYS_64BIT
 349 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 350 #else
 351 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 352 #endif
 353 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 354 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 355                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 356                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 357                                 | CSPR_V)
 358 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 359
 360 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 361                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 362                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 363                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 364                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 365                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 366                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 367
 368 #define CONFIG_SYS_NAND_ONFI_DETECTION
 369
 370 /* ONFI NAND Flash mode0 Timing Params */
 371 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 372                                         FTIM0_NAND_TWP(0x18)   | \
 373                                         FTIM0_NAND_TWCHT(0x07) | \
 374                                         FTIM0_NAND_TWH(0x0a))
 375 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 376                                         FTIM1_NAND_TWBE(0x39)  | \
 377                                         FTIM1_NAND_TRR(0x0e)   | \
 378                                         FTIM1_NAND_TRP(0x18))
 379 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 380                                         FTIM2_NAND_TREH(0x0a) | \
 381                                         FTIM2_NAND_TWHRE(0x1e))
 382 #define CONFIG_SYS_NAND_FTIM3           0x0
 383
 384 #define CONFIG_SYS_NAND_DDR_LAW         11
 385 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 386 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 387 #define CONFIG_CMD_NAND
 388
 389 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 390
 391 #if defined(CONFIG_NAND)
 392 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 393 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 394 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 395 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 396 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 397 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 398 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 399 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 400 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 401 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 402 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 403 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 404 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 405 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 406 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 407 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 408 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 409 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 410 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 411 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 412 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 413 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 414 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 415 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 416 #else
 417 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 418 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 419 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 420 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 421 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 422 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 423 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 424 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 425 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 426 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 427 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 428 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 429 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 430 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 431 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 432 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 433 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 434 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 435 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 436 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 437 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 438 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 439 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 440 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 441 #endif
 442
 443 #ifdef CONFIG_SPL_BUILD
 444 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 445 #else
 446 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 447 #endif
 448
 449 #if defined(CONFIG_RAMBOOT_PBL)
 450 #define CONFIG_SYS_RAMBOOT
 451 #endif
 452
 453 #define CONFIG_BOARD_EARLY_INIT_R
 454 #define CONFIG_MISC_INIT_R
 455
 456 #define CONFIG_HWCONFIG
 457
 458 /* define to use L1 as initial stack */
 459 #define CONFIG_L1_INIT_RAM
 460 #define CONFIG_SYS_INIT_RAM_LOCK
 461 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 462 #ifdef CONFIG_PHYS_64BIT
 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 465 /* The assembler doesn't like typecast */
 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 467         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 468           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 469 #else
 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 473 #endif
 474 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 475
 476 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 477                                         GENERATED_GBL_DATA_SIZE)
 478 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 479
 480 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 481 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 482
 483 /* Serial Port */
 484 #define CONFIG_CONS_INDEX       1
 485 #define CONFIG_SYS_NS16550_SERIAL
 486 #define CONFIG_SYS_NS16550_REG_SIZE     1
 487 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 488
 489 #define CONFIG_SYS_BAUDRATE_TABLE       \
 490         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 491
 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 494 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 495 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 496
 497 /* Video */
 498 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 499 #define CONFIG_FSL_DIU_FB
 500 #ifdef CONFIG_FSL_DIU_FB
 501 #define CONFIG_FSL_DIU_CH7301
 502 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 503 #define CONFIG_CMD_BMP
 504 #define CONFIG_VIDEO_LOGO
 505 #define CONFIG_VIDEO_BMP_LOGO
 506 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 507 /*
 508  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 509  * disable empty flash sector detection, which is I/O-intensive.
 510  */
 511 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 512 #endif
 513 #endif
 514
 515 /* I2C */
 516 #define CONFIG_SYS_I2C
 517 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 518 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 519 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 520 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 521 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 522 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 523 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 524
 525 #define I2C_MUX_PCA_ADDR                0x77
 526 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 527 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 528 #define I2C_RETIMER_ADDR                0x18
 529
 530 /* I2C bus multiplexer */
 531 #define I2C_MUX_CH_DEFAULT      0x8
 532 #define I2C_MUX_CH_DIU          0xC
 533 #define I2C_MUX_CH5             0xD
 534 #define I2C_MUX_CH7             0xF
 535
 536 /* LDI/DVI Encoder for display */
 537 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 538 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 539
 540 /*
 541  * RTC configuration
 542  */
 543 #define RTC
 544 #define CONFIG_RTC_DS3231       1
 545 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 546
 547 /*
 548  * eSPI - Enhanced SPI
 549  */
 550 #ifndef CONFIG_SPL_BUILD
 551 #endif
 552 #define CONFIG_SPI_FLASH_BAR
 553 #define CONFIG_SF_DEFAULT_SPEED  10000000
 554 #define CONFIG_SF_DEFAULT_MODE    0
 555
 556 /*
 557  * General PCIe
 558  * Memory space is mapped 1-1, but I/O space must start from 0.
 559  */
 560 #define CONFIG_PCIE1            /* PCIE controller 1 */
 561 #define CONFIG_PCIE2            /* PCIE controller 2 */
 562 #define CONFIG_PCIE3            /* PCIE controller 3 */
 563 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 564 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 565 #define CONFIG_PCI_INDIRECT_BRIDGE
 566
 567 #ifdef CONFIG_PCI
 568 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 569 #ifdef CONFIG_PCIE1
 570 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 571 #ifdef CONFIG_PHYS_64BIT
 572 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 573 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 574 #else
 575 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 576 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 577 #endif
 578 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 579 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 580 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 581 #ifdef CONFIG_PHYS_64BIT
 582 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 583 #else
 584 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 585 #endif
 586 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 587 #endif
 588
 589 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 590 #ifdef CONFIG_PCIE2
 591 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 592 #ifdef CONFIG_PHYS_64BIT
 593 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 594 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 595 #else
 596 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 597 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 598 #endif
 599 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 600 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 601 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 602 #ifdef CONFIG_PHYS_64BIT
 603 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 604 #else
 605 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 606 #endif
 607 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 608 #endif
 609
 610 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 611 #ifdef CONFIG_PCIE3
 612 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 613 #ifdef CONFIG_PHYS_64BIT
 614 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 615 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 616 #else
 617 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 618 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 619 #endif
 620 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 621 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 622 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 623 #ifdef CONFIG_PHYS_64BIT
 624 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 625 #else
 626 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 627 #endif
 628 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 629 #endif
 630
 631 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 632 #define CONFIG_DOS_PARTITION
 633 #endif  /* CONFIG_PCI */
 634
 635 /*
 636  *SATA
 637  */
 638 #define CONFIG_FSL_SATA_V2
 639 #ifdef CONFIG_FSL_SATA_V2
 640 #define CONFIG_LIBATA
 641 #define CONFIG_FSL_SATA
 642 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 643 #define CONFIG_SATA1
 644 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 645 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 646 #define CONFIG_LBA48
 647 #define CONFIG_CMD_SATA
 648 #define CONFIG_DOS_PARTITION
 649 #endif
 650
 651 /*
 652  * USB
 653  */
 654 #define CONFIG_HAS_FSL_DR_USB
 655
 656 #ifdef CONFIG_HAS_FSL_DR_USB
 657 #define CONFIG_USB_EHCI
 658 #define CONFIG_USB_EHCI_FSL
 659 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 660 #endif
 661
 662 /*
 663  * SDHC
 664  */
 665 #define CONFIG_MMC
 666 #ifdef CONFIG_MMC
 667 #define CONFIG_FSL_ESDHC
 668 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 669 #define CONFIG_GENERIC_MMC
 670 #define CONFIG_DOS_PARTITION
 671 #endif
 672
 673 /* Qman/Bman */
 674 #ifndef CONFIG_NOBQFMAN
 675 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 676 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 677 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 678 #ifdef CONFIG_PHYS_64BIT
 679 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 680 #else
 681 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 682 #endif
 683 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 684 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 685 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 686 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 687 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 688 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 689                                         CONFIG_SYS_BMAN_CENA_SIZE)
 690 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 691 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 692 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 693 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 694 #ifdef CONFIG_PHYS_64BIT
 695 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 696 #else
 697 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 698 #endif
 699 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 700 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 701 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 702 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 703 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 704 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 705                                         CONFIG_SYS_QMAN_CENA_SIZE)
 706 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 707 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 708
 709 #define CONFIG_SYS_DPAA_FMAN
 710
 711 #define CONFIG_QE
 712 #define CONFIG_U_QE
 713 /* Default address of microcode for the Linux FMan driver */
 714 #if defined(CONFIG_SPIFLASH)
 715 /*
 716  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 717  * env, so we got 0x110000.
 718  */
 719 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 720 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 721 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 722 #elif defined(CONFIG_SDCARD)
 723 /*
 724  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 725  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 726  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 727  */
 728 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 729 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 730 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 731 #elif defined(CONFIG_NAND)
 732 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 733 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 734 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 735 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 736 /*
 737  * Slave has no ucode locally, it can fetch this from remote. When implementing
 738  * in two corenet boards, slave's ucode could be stored in master's memory
 739  * space, the address can be mapped from slave TLB->slave LAW->
 740  * slave SRIO or PCIE outbound window->master inbound window->
 741  * master LAW->the ucode address in master's memory space.
 742  */
 743 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 744 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 745 #else
 746 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 747 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 748 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 749 #endif
 750 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 751 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 752 #endif /* CONFIG_NOBQFMAN */
 753
 754 #ifdef CONFIG_SYS_DPAA_FMAN
 755 #define CONFIG_FMAN_ENET
 756 #define CONFIG_PHYLIB_10G
 757 #define CONFIG_PHY_VITESSE
 758 #define CONFIG_PHY_REALTEK
 759 #define CONFIG_PHY_TERANETICS
 760 #define RGMII_PHY1_ADDR         0x1
 761 #define RGMII_PHY2_ADDR         0x2
 762 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 763 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 764 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 765 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 766 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 767 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 768 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 769 #endif
 770
 771 #ifdef CONFIG_FMAN_ENET
 772 #define CONFIG_MII              /* MII PHY management */
 773 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 774 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 775 #endif
 776
 777 /*
 778  * Dynamic MTD Partition support with mtdparts
 779  */
 780 #ifndef CONFIG_SYS_NO_FLASH
 781 #define CONFIG_MTD_DEVICE
 782 #define CONFIG_MTD_PARTITIONS
 783 #define CONFIG_CMD_MTDPARTS
 784 #define CONFIG_FLASH_CFI_MTD
 785 #define MTDIDS_DEFAULT    "nor0=fe8000000.nor,nand0=fff800000.flash," \
 786                           "spi0=spife110000.0"
 787 #define MTDPARTS_DEFAULT  "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 788                           "128k(dtb),96m(fs),-(user);"\
 789                           "fff800000.flash:2m(uboot),9m(kernel),"\
 790                           "128k(dtb),96m(fs),-(user);spife110000.0:" \
 791                           "2m(uboot),9m(kernel),128k(dtb),-(user)"
 792 #endif
 793
 794 /*
 795  * Environment
 796  */
 797 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 798 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 799
 800 /*
 801  * Command line configuration.
 802  */
 803 #define CONFIG_CMD_DATE
 804 #define CONFIG_CMD_EEPROM
 805 #define CONFIG_CMD_ERRATA
 806 #define CONFIG_CMD_IRQ
 807 #define CONFIG_CMD_REGINFO
 808
 809 #ifdef CONFIG_PCI
 810 #define CONFIG_CMD_PCI
 811 #endif
 812
 813 /*
 814  * Miscellaneous configurable options
 815  */
 816 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 817 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 818 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 819 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 820 #ifdef CONFIG_CMD_KGDB
 821 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 822 #else
 823 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 824 #endif
 825 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 826 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 827 #define CONFIG_SYS_BARGSIZE  CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 828
 829 /*
 830  * For booting Linux, the board info and command line data
 831  * have to be in the first 64 MB of memory, since this is
 832  * the maximum mapped by the Linux kernel during initialization.
 833  */
 834 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 835 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 836
 837 #ifdef CONFIG_CMD_KGDB
 838 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 839 #endif
 840
 841 /*
 842  * Environment Configuration
 843  */
 844 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 845 #define CONFIG_BOOTFILE         "uImage"
 846 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 847 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 848 #define CONFIG_BAUDRATE         115200
 849 #define __USB_PHY_TYPE          utmi
 850
 851 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 852         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 853         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 854         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 855         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 856         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 857         "netdev=eth0\0"                                         \
 858         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 859         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 860         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 861         "tftpflash=tftpboot $loadaddr $uboot && "               \
 862         "protect off $ubootaddr +$filesize && "                 \
 863         "erase $ubootaddr +$filesize && "                       \
 864         "cp.b $loadaddr $ubootaddr $filesize && "               \
 865         "protect on $ubootaddr +$filesize && "                  \
 866         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 867         "consoledev=ttyS0\0"                                    \
 868         "ramdiskaddr=2000000\0"                                 \
 869         "fdtaddr=d00000\0"                                      \
 870         "bdev=sda3\0"
 871
 872 #define CONFIG_LINUX                                    \
 873         "setenv bootargs root=/dev/ram rw "             \
 874         "console=$consoledev,$baudrate $othbootargs;"   \
 875         "setenv ramdiskaddr 0x02000000;"                \
 876         "setenv fdtaddr 0x00c00000;"                    \
 877         "setenv loadaddr 0x1000000;"                    \
 878         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 879
 880 #define CONFIG_NFSBOOTCOMMAND                   \
 881         "setenv bootargs root=/dev/nfs rw "     \
 882         "nfsroot=$serverip:$rootpath "          \
 883         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 884         "console=$consoledev,$baudrate $othbootargs;"   \
 885         "tftp $loadaddr $bootfile;"             \
 886         "tftp $fdtaddr $fdtfile;"               \
 887         "bootm $loadaddr - $fdtaddr"
 888
 889 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 890
 891 /* Hash command with SHA acceleration supported in hardware */
 892 #ifdef CONFIG_FSL_CAAM
 893 #define CONFIG_CMD_HASH
 894 #define CONFIG_SHA_HW_ACCEL
 895 #endif
 896
 897 #include <asm/fsl_secure_boot.h>
 898
 899 #endif  /* __T1024QDS_H */