include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T1024/T1023 QDS board configuration file
   9  */
  10
  11 #ifndef __T1024QDS_H
  12 #define __T1024QDS_H
  13
  14 /* High Level Configuration Options */
  15 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  16 #define CONFIG_ENABLE_36BIT_PHYS
  17
  18 #ifdef CONFIG_PHYS_64BIT
  19 #define CONFIG_ADDR_MAP         1
  20 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  21 #endif
  22
  23 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #define CONFIG_ENV_OVERWRITE
  27
  28 #define CONFIG_DEEP_SLEEP
  29
  30 #ifdef CONFIG_RAMBOOT_PBL
  31 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_MTD_RAW_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  49 #endif
  50
  51 #ifdef CONFIG_SPIFLASH
  52 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  53 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  58 #ifndef CONFIG_SPL_BUILD
  59 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  60 #endif
  61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  62 #endif
  63
  64 #ifdef CONFIG_SDCARD
  65 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  66 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  67 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  68 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  70 #ifndef CONFIG_SPL_BUILD
  71 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  72 #endif
  73 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  74 #endif
  75
  76 #endif /* CONFIG_RAMBOOT_PBL */
  77
  78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  79 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  80 #endif
  81
  82 /* PCIe Boot - Master */
  83 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  84 /*
  85  * for slave u-boot IMAGE instored in master memory space,
  86  * PHYS must be aligned based on the SIZE
  87  */
  88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
  89 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
  90 #ifdef CONFIG_PHYS_64BIT
  91 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
  92 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
  93 #else
  94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
  95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
  96 #endif
  97 /*
  98  * for slave UCODE and ENV instored in master memory space,
  99  * PHYS must be aligned based on the SIZE
 100  */
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 103 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 104 #else
 105 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 106 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 107 #endif
 108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 109 /* slave core release by master*/
 110 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 111 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 112
 113 /* PCIe Boot - Slave */
 114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 117                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 118 /* Set 1M boot space for PCIe boot */
 119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 121                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 123 #endif
 124
 125 #if defined(CONFIG_SPIFLASH)
 126 #elif defined(CONFIG_SDCARD)
 127 #define CONFIG_SYS_MMC_ENV_DEV          0
 128 #endif
 129
 130 #ifndef __ASSEMBLY__
 131 unsigned long get_board_sys_clk(void);
 132 unsigned long get_board_ddr_clk(void);
 133 #endif
 134
 135 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 136 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 137
 138 /*
 139  * These can be toggled for performance analysis, otherwise use default.
 140  */
 141 #define CONFIG_SYS_CACHE_STASHING
 142 #define CONFIG_BACKSIDE_L2_CACHE
 143 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 144 #define CONFIG_BTB                      /* toggle branch predition */
 145 #define CONFIG_DDR_ECC
 146 #ifdef CONFIG_DDR_ECC
 147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 148 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 149 #endif
 150
 151 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 152 #define CONFIG_SYS_MEMTEST_END          0x00400000
 153
 154 /*
 155  *  Config the L3 Cache as L3 SRAM
 156  */
 157 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 158 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 159 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 160 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 161 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 162 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 163 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 164
 165 #ifdef CONFIG_PHYS_64BIT
 166 #define CONFIG_SYS_DCSRBAR              0xf0000000
 167 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 168 #endif
 169
 170 /* EEPROM */
 171 #define CONFIG_ID_EEPROM
 172 #define CONFIG_SYS_I2C_EEPROM_NXID
 173 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 178
 179 /*
 180  * DDR Setup
 181  */
 182 #define CONFIG_VERY_BIG_RAM
 183 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 184 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 185 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 186 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 187 #define CONFIG_DDR_SPD
 188
 189 #define CONFIG_SYS_SPD_BUS_NUM  0
 190 #define SPD_EEPROM_ADDRESS      0x51
 191
 192 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 193
 194 /*
 195  * IFC Definitions
 196  */
 197 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 198 #ifdef CONFIG_PHYS_64BIT
 199 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 200 #else
 201 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 202 #endif
 203
 204 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 205 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 206                                 + 0x8000000) | \
 207                                 CSPR_PORT_SIZE_16 | \
 208                                 CSPR_MSEL_NOR | \
 209                                 CSPR_V)
 210 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 211 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 212                                 CSPR_PORT_SIZE_16 | \
 213                                 CSPR_MSEL_NOR | \
 214                                 CSPR_V)
 215 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 216 /* NOR Flash Timing Params */
 217 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 218 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 219                                 FTIM0_NOR_TEADC(0x5) | \
 220                                 FTIM0_NOR_TEAHC(0x5))
 221 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 222                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 223                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 224 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 225                                 FTIM2_NOR_TCH(0x4) | \
 226                                 FTIM2_NOR_TWPH(0x0E) | \
 227                                 FTIM2_NOR_TWP(0x1c))
 228 #define CONFIG_SYS_NOR_FTIM3    0x0
 229
 230 #define CONFIG_SYS_FLASH_QUIET_TEST
 231 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 232
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 236 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 237
 238 #define CONFIG_SYS_FLASH_EMPTY_INFO
 239 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 240                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 241 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 242 #define QIXIS_BASE              0xffdf0000
 243 #ifdef CONFIG_PHYS_64BIT
 244 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 245 #else
 246 #define QIXIS_BASE_PHYS         QIXIS_BASE
 247 #endif
 248 #define QIXIS_LBMAP_SWITCH              0x06
 249 #define QIXIS_LBMAP_MASK                0x0f
 250 #define QIXIS_LBMAP_SHIFT               0
 251 #define QIXIS_LBMAP_DFLTBANK            0x00
 252 #define QIXIS_LBMAP_ALTBANK             0x04
 253 #define QIXIS_RST_CTL_RESET             0x31
 254 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 255 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 256 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 257 #define QIXIS_RST_FORCE_MEM             0x01
 258
 259 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 260 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 261                                 | CSPR_PORT_SIZE_8 \
 262                                 | CSPR_MSEL_GPCM \
 263                                 | CSPR_V)
 264 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 265 #define CONFIG_SYS_CSOR3        0x0
 266 /* QIXIS Timing parameters for IFC CS3 */
 267 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 268                                         FTIM0_GPCM_TEADC(0x0e) | \
 269                                         FTIM0_GPCM_TEAHC(0x0e))
 270 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 271                                         FTIM1_GPCM_TRAD(0x3f))
 272 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 273                                         FTIM2_GPCM_TCH(0x8) | \
 274                                         FTIM2_GPCM_TWP(0x1f))
 275 #define CONFIG_SYS_CS3_FTIM3            0x0
 276
 277 #define CONFIG_NAND_FSL_IFC
 278 #define CONFIG_SYS_NAND_BASE            0xff800000
 279 #ifdef CONFIG_PHYS_64BIT
 280 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 281 #else
 282 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 283 #endif
 284 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 285 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 286                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 287                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 288                                 | CSPR_V)
 289 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 290
 291 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 292                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 293                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 294                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 295                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 296                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 297                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 298
 299 #define CONFIG_SYS_NAND_ONFI_DETECTION
 300
 301 /* ONFI NAND Flash mode0 Timing Params */
 302 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 303                                         FTIM0_NAND_TWP(0x18)   | \
 304                                         FTIM0_NAND_TWCHT(0x07) | \
 305                                         FTIM0_NAND_TWH(0x0a))
 306 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 307                                         FTIM1_NAND_TWBE(0x39)  | \
 308                                         FTIM1_NAND_TRR(0x0e)   | \
 309                                         FTIM1_NAND_TRP(0x18))
 310 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 311                                         FTIM2_NAND_TREH(0x0a) | \
 312                                         FTIM2_NAND_TWHRE(0x1e))
 313 #define CONFIG_SYS_NAND_FTIM3           0x0
 314
 315 #define CONFIG_SYS_NAND_DDR_LAW         11
 316 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 317 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 318
 319 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 320
 321 #if defined(CONFIG_MTD_RAW_NAND)
 322 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 323 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 324 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 325 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 326 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 327 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 328 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 329 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 330 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 331 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 332 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 333 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 334 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 335 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 336 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 337 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 338 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 339 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 340 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 341 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 342 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 343 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 344 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 345 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 346 #else
 347 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 348 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 349 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 350 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 351 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 352 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 353 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 354 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 355 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 356 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 357 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 358 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 359 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 360 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 361 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 362 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 363 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 364 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 365 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 366 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 367 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 368 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 369 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 370 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 371 #endif
 372
 373 #ifdef CONFIG_SPL_BUILD
 374 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 375 #else
 376 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 377 #endif
 378
 379 #if defined(CONFIG_RAMBOOT_PBL)
 380 #define CONFIG_SYS_RAMBOOT
 381 #endif
 382
 383 #define CONFIG_HWCONFIG
 384
 385 /* define to use L1 as initial stack */
 386 #define CONFIG_L1_INIT_RAM
 387 #define CONFIG_SYS_INIT_RAM_LOCK
 388 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 389 #ifdef CONFIG_PHYS_64BIT
 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 392 /* The assembler doesn't like typecast */
 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 394         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 395           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 396 #else
 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 400 #endif
 401 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 402
 403 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 404                                         GENERATED_GBL_DATA_SIZE)
 405 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 406
 407 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 408 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 409
 410 /* Serial Port */
 411 #define CONFIG_SYS_NS16550_SERIAL
 412 #define CONFIG_SYS_NS16550_REG_SIZE     1
 413 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 414
 415 #define CONFIG_SYS_BAUDRATE_TABLE       \
 416         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 417
 418 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 419 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 420 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 421 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 422
 423 /* Video */
 424 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 425 #define CONFIG_FSL_DIU_FB
 426 #ifdef CONFIG_FSL_DIU_FB
 427 #define CONFIG_FSL_DIU_CH7301
 428 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 429 #define CONFIG_VIDEO_LOGO
 430 #define CONFIG_VIDEO_BMP_LOGO
 431 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 432 /*
 433  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 434  * disable empty flash sector detection, which is I/O-intensive.
 435  */
 436 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 437 #endif
 438 #endif
 439
 440 /* I2C */
 441 #ifndef CONFIG_DM_I2C
 442 #define CONFIG_SYS_I2C
 443 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 444 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 445 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 446 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 447 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 448 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 449 #else
 450 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 451 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 452 #endif
 453
 454 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 455
 456 #define I2C_MUX_PCA_ADDR                0x77
 457 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 458 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 459 #define I2C_RETIMER_ADDR                0x18
 460
 461 /* I2C bus multiplexer */
 462 #define I2C_MUX_CH_DEFAULT      0x8
 463 #define I2C_MUX_CH_DIU          0xC
 464 #define I2C_MUX_CH5             0xD
 465 #define I2C_MUX_CH7             0xF
 466
 467 /* LDI/DVI Encoder for display */
 468 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 469 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 470 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
 471
 472 /*
 473  * RTC configuration
 474  */
 475 #define RTC
 476 #define CONFIG_RTC_DS3231       1
 477 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 478
 479 /*
 480  * eSPI - Enhanced SPI
 481  */
 482
 483 /*
 484  * General PCIe
 485  * Memory space is mapped 1-1, but I/O space must start from 0.
 486  */
 487 #define CONFIG_PCIE1            /* PCIE controller 1 */
 488 #define CONFIG_PCIE2            /* PCIE controller 2 */
 489 #define CONFIG_PCIE3            /* PCIE controller 3 */
 490 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 491 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 492 #define CONFIG_PCI_INDIRECT_BRIDGE
 493
 494 #ifdef CONFIG_PCI
 495 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 496 #ifdef CONFIG_PCIE1
 497 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 498 #ifdef CONFIG_PHYS_64BIT
 499 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 500 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 501 #else
 502 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 503 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 504 #endif
 505 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 506 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 507 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 508 #ifdef CONFIG_PHYS_64BIT
 509 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 510 #else
 511 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 512 #endif
 513 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 514 #endif
 515
 516 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 517 #ifdef CONFIG_PCIE2
 518 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 519 #ifdef CONFIG_PHYS_64BIT
 520 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 521 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 522 #else
 523 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 524 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 525 #endif
 526 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 527 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 528 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 529 #ifdef CONFIG_PHYS_64BIT
 530 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 531 #else
 532 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 533 #endif
 534 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 535 #endif
 536
 537 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 538 #ifdef CONFIG_PCIE3
 539 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 540 #ifdef CONFIG_PHYS_64BIT
 541 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 542 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 543 #else
 544 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 545 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 546 #endif
 547 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 548 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 549 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 550 #ifdef CONFIG_PHYS_64BIT
 551 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 552 #else
 553 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 554 #endif
 555 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 556 #endif
 557
 558 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 559 #endif  /* CONFIG_PCI */
 560
 561 /*
 562  *SATA
 563  */
 564 #define CONFIG_FSL_SATA_V2
 565 #ifdef CONFIG_FSL_SATA_V2
 566 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 567 #define CONFIG_SATA1
 568 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 569 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 570 #define CONFIG_LBA48
 571 #endif
 572
 573 /*
 574  * USB
 575  */
 576 #define CONFIG_HAS_FSL_DR_USB
 577
 578 #ifdef CONFIG_HAS_FSL_DR_USB
 579 #define CONFIG_USB_EHCI_FSL
 580 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 581 #endif
 582
 583 /*
 584  * SDHC
 585  */
 586 #ifdef CONFIG_MMC
 587 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 588 #endif
 589
 590 /* Qman/Bman */
 591 #ifndef CONFIG_NOBQFMAN
 592 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 593 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 594 #ifdef CONFIG_PHYS_64BIT
 595 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 596 #else
 597 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 598 #endif
 599 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 600 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 601 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 602 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 603 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 604 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 605                                         CONFIG_SYS_BMAN_CENA_SIZE)
 606 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 607 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 608 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 609 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 610 #ifdef CONFIG_PHYS_64BIT
 611 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 612 #else
 613 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 614 #endif
 615 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 616 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 617 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 618 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 619 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 620 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 621                                         CONFIG_SYS_QMAN_CENA_SIZE)
 622 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 623 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 624
 625 #define CONFIG_SYS_DPAA_FMAN
 626
 627 /* Default address of microcode for the Linux FMan driver */
 628 #if defined(CONFIG_SPIFLASH)
 629 /*
 630  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 631  * env, so we got 0x110000.
 632  */
 633 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 634 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 635 #elif defined(CONFIG_SDCARD)
 636 /*
 637  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 638  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 639  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 640  */
 641 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 642 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 643 #elif defined(CONFIG_MTD_RAW_NAND)
 644 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 645 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 646 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 647 /*
 648  * Slave has no ucode locally, it can fetch this from remote. When implementing
 649  * in two corenet boards, slave's ucode could be stored in master's memory
 650  * space, the address can be mapped from slave TLB->slave LAW->
 651  * slave SRIO or PCIE outbound window->master inbound window->
 652  * master LAW->the ucode address in master's memory space.
 653  */
 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 655 #else
 656 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 657 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 658 #endif
 659 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 660 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 661 #endif /* CONFIG_NOBQFMAN */
 662
 663 #ifdef CONFIG_SYS_DPAA_FMAN
 664 #define RGMII_PHY1_ADDR         0x1
 665 #define RGMII_PHY2_ADDR         0x2
 666 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 667 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 668 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 669 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 670 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 671 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 672 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 673 #endif
 674
 675 #ifdef CONFIG_FMAN_ENET
 676 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 677 #endif
 678
 679 /*
 680  * Dynamic MTD Partition support with mtdparts
 681  */
 682
 683 /*
 684  * Environment
 685  */
 686 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 687 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 688
 689 /*
 690  * Miscellaneous configurable options
 691  */
 692 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 693
 694 /*
 695  * For booting Linux, the board info and command line data
 696  * have to be in the first 64 MB of memory, since this is
 697  * the maximum mapped by the Linux kernel during initialization.
 698  */
 699 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 700 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 701
 702 #ifdef CONFIG_CMD_KGDB
 703 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 704 #endif
 705
 706 /*
 707  * Environment Configuration
 708  */
 709 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 710 #define CONFIG_BOOTFILE         "uImage"
 711 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 712 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 713 #define __USB_PHY_TYPE          utmi
 714
 715 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 716         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 717         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 718         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 719         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 720         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 721         "netdev=eth0\0"                                         \
 722         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 723         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 724         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 725         "tftpflash=tftpboot $loadaddr $uboot && "               \
 726         "protect off $ubootaddr +$filesize && "                 \
 727         "erase $ubootaddr +$filesize && "                       \
 728         "cp.b $loadaddr $ubootaddr $filesize && "               \
 729         "protect on $ubootaddr +$filesize && "                  \
 730         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 731         "consoledev=ttyS0\0"                                    \
 732         "ramdiskaddr=2000000\0"                                 \
 733         "fdtaddr=d00000\0"                                      \
 734         "bdev=sda3\0"
 735
 736 #define CONFIG_LINUX                                    \
 737         "setenv bootargs root=/dev/ram rw "             \
 738         "console=$consoledev,$baudrate $othbootargs;"   \
 739         "setenv ramdiskaddr 0x02000000;"                \
 740         "setenv fdtaddr 0x00c00000;"                    \
 741         "setenv loadaddr 0x1000000;"                    \
 742         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 743
 744 #define CONFIG_NFSBOOTCOMMAND                   \
 745         "setenv bootargs root=/dev/nfs rw "     \
 746         "nfsroot=$serverip:$rootpath "          \
 747         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 748         "console=$consoledev,$baudrate $othbootargs;"   \
 749         "tftp $loadaddr $bootfile;"             \
 750         "tftp $fdtaddr $fdtfile;"               \
 751         "bootm $loadaddr - $fdtaddr"
 752
 753 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 754
 755 #include <asm/fsl_secure_boot.h>
 756
 757 #endif  /* __T1024QDS_H */