include/configs/T102xQDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T1024/T1023 QDS board configuration file
   8  */
   9
  10 #ifndef __T1024QDS_H
  11 #define __T1024QDS_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_ENABLE_36BIT_PHYS
  16
  17 #ifdef CONFIG_PHYS_64BIT
  18 #define CONFIG_ADDR_MAP         1
  19 #define CONFIG_SYS_NUM_ADDR_MAP 64      /* number of TLB1 entries */
  20 #endif
  21
  22 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  23 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  24
  25 #define CONFIG_ENV_OVERWRITE
  26
  27 #define CONFIG_DEEP_SLEEP
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
  31 #define CONFIG_SPL_FLUSH_IMAGE
  32 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  33 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  34 #define CONFIG_SPL_PAD_TO               0x40000
  35 #define CONFIG_SPL_MAX_SIZE             0x28000
  36 #define RESET_VECTOR_OFFSET             0x27FFC
  37 #define BOOT_PAGE_OFFSET                0x27000
  38 #ifdef CONFIG_SPL_BUILD
  39 #define CONFIG_SPL_SKIP_RELOCATE
  40 #define CONFIG_SPL_COMMON_INIT_DDR
  41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  42 #endif
  43
  44 #ifdef CONFIG_NAND
  45 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  46 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  48 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
  51 #define CONFIG_SPL_NAND_BOOT
  52 #endif
  53
  54 #ifdef CONFIG_SPIFLASH
  55 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  56 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  61 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  62 #ifndef CONFIG_SPL_BUILD
  63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  64 #endif
  65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
  66 #define CONFIG_SPL_SPI_BOOT
  67 #endif
  68
  69 #ifdef CONFIG_SDCARD
  70 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  71 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  72 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  73 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  74 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  75 #define CONFIG_SYS_LDSCRIPT             "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  76 #ifndef CONFIG_SPL_BUILD
  77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  78 #endif
  79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
  80 #define CONFIG_SPL_MMC_BOOT
  81 #endif
  82
  83 #endif /* CONFIG_RAMBOOT_PBL */
  84
  85 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  86 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  87 #endif
  88
  89 #ifdef CONFIG_MTD_NOR_FLASH
  90 #define CONFIG_FLASH_CFI_DRIVER
  91 #define CONFIG_SYS_FLASH_CFI
  92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  93 #endif
  94
  95 /* PCIe Boot - Master */
  96 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  97 /*
  98  * for slave u-boot IMAGE instored in master memory space,
  99  * PHYS must be aligned based on the SIZE
 100  */
 101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 102 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 105 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 106 #else
 107 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
 108 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
 109 #endif
 110 /*
 111  * for slave UCODE and ENV instored in master memory space,
 112  * PHYS must be aligned based on the SIZE
 113  */
 114 #ifdef CONFIG_PHYS_64BIT
 115 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 116 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
 117 #else
 118 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
 119 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
 120 #endif
 121 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
 122 /* slave core release by master*/
 123 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 124 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 125
 126 /* PCIe Boot - Slave */
 127 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 128 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 130                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 131 /* Set 1M boot space for PCIe boot */
 132 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 133 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
 134                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 135 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 136 #endif
 137
 138 #if defined(CONFIG_SPIFLASH)
 139 #define CONFIG_SYS_EXTRA_ENV_RELOC
 140 #define CONFIG_ENV_SPI_BUS              0
 141 #define CONFIG_ENV_SPI_CS               0
 142 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 143 #define CONFIG_ENV_SPI_MODE             0
 144 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 145 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 146 #define CONFIG_ENV_SECT_SIZE            0x10000
 147 #elif defined(CONFIG_SDCARD)
 148 #define CONFIG_SYS_EXTRA_ENV_RELOC
 149 #define CONFIG_SYS_MMC_ENV_DEV          0
 150 #define CONFIG_ENV_SIZE                 0x2000
 151 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 152 #elif defined(CONFIG_NAND)
 153 #define CONFIG_SYS_EXTRA_ENV_RELOC
 154 #define CONFIG_ENV_SIZE                 0x2000
 155 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 156 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 157 #define CONFIG_ENV_ADDR         0xffe20000
 158 #define CONFIG_ENV_SIZE         0x2000
 159 #elif defined(CONFIG_ENV_IS_NOWHERE)
 160 #define CONFIG_ENV_SIZE         0x2000
 161 #else
 162 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 163 #define CONFIG_ENV_SIZE         0x2000
 164 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 165 #endif
 166
 167 #ifndef __ASSEMBLY__
 168 unsigned long get_board_sys_clk(void);
 169 unsigned long get_board_ddr_clk(void);
 170 #endif
 171
 172 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 173 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 174
 175 /*
 176  * These can be toggled for performance analysis, otherwise use default.
 177  */
 178 #define CONFIG_SYS_CACHE_STASHING
 179 #define CONFIG_BACKSIDE_L2_CACHE
 180 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 181 #define CONFIG_BTB                      /* toggle branch predition */
 182 #define CONFIG_DDR_ECC
 183 #ifdef CONFIG_DDR_ECC
 184 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 185 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 186 #endif
 187
 188 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 189 #define CONFIG_SYS_MEMTEST_END          0x00400000
 190
 191 /*
 192  *  Config the L3 Cache as L3 SRAM
 193  */
 194 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 195 #define CONFIG_SYS_L3_SIZE              (256 << 10)
 196 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 197 #ifdef CONFIG_RAMBOOT_PBL
 198 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 199 #endif
 200 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 201 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 202 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 203
 204 #ifdef CONFIG_PHYS_64BIT
 205 #define CONFIG_SYS_DCSRBAR              0xf0000000
 206 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 207 #endif
 208
 209 /* EEPROM */
 210 #define CONFIG_ID_EEPROM
 211 #define CONFIG_SYS_I2C_EEPROM_NXID
 212 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 217
 218 /*
 219  * DDR Setup
 220  */
 221 #define CONFIG_VERY_BIG_RAM
 222 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 223 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 224 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 225 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 226 #define CONFIG_DDR_SPD
 227
 228 #define CONFIG_SYS_SPD_BUS_NUM  0
 229 #define SPD_EEPROM_ADDRESS      0x51
 230
 231 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 232
 233 /*
 234  * IFC Definitions
 235  */
 236 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 237 #ifdef CONFIG_PHYS_64BIT
 238 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 239 #else
 240 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 241 #endif
 242
 243 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 244 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 245                                 + 0x8000000) | \
 246                                 CSPR_PORT_SIZE_16 | \
 247                                 CSPR_MSEL_NOR | \
 248                                 CSPR_V)
 249 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 250 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 251                                 CSPR_PORT_SIZE_16 | \
 252                                 CSPR_MSEL_NOR | \
 253                                 CSPR_V)
 254 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 255 /* NOR Flash Timing Params */
 256 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 257 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 258                                 FTIM0_NOR_TEADC(0x5) | \
 259                                 FTIM0_NOR_TEAHC(0x5))
 260 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 261                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 262                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 263 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 264                                 FTIM2_NOR_TCH(0x4) | \
 265                                 FTIM2_NOR_TWPH(0x0E) | \
 266                                 FTIM2_NOR_TWP(0x1c))
 267 #define CONFIG_SYS_NOR_FTIM3    0x0
 268
 269 #define CONFIG_SYS_FLASH_QUIET_TEST
 270 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 271
 272 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 273 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 274 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 275 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 276
 277 #define CONFIG_SYS_FLASH_EMPTY_INFO
 278 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 279                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 280 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 281 #define QIXIS_BASE              0xffdf0000
 282 #ifdef CONFIG_PHYS_64BIT
 283 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 284 #else
 285 #define QIXIS_BASE_PHYS         QIXIS_BASE
 286 #endif
 287 #define QIXIS_LBMAP_SWITCH              0x06
 288 #define QIXIS_LBMAP_MASK                0x0f
 289 #define QIXIS_LBMAP_SHIFT               0
 290 #define QIXIS_LBMAP_DFLTBANK            0x00
 291 #define QIXIS_LBMAP_ALTBANK             0x04
 292 #define QIXIS_RST_CTL_RESET             0x31
 293 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 294 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 295 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 296 #define QIXIS_RST_FORCE_MEM             0x01
 297
 298 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 299 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 300                                 | CSPR_PORT_SIZE_8 \
 301                                 | CSPR_MSEL_GPCM \
 302                                 | CSPR_V)
 303 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 304 #define CONFIG_SYS_CSOR3        0x0
 305 /* QIXIS Timing parameters for IFC CS3 */
 306 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 307                                         FTIM0_GPCM_TEADC(0x0e) | \
 308                                         FTIM0_GPCM_TEAHC(0x0e))
 309 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 310                                         FTIM1_GPCM_TRAD(0x3f))
 311 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 312                                         FTIM2_GPCM_TCH(0x8) | \
 313                                         FTIM2_GPCM_TWP(0x1f))
 314 #define CONFIG_SYS_CS3_FTIM3            0x0
 315
 316 #define CONFIG_NAND_FSL_IFC
 317 #define CONFIG_SYS_NAND_BASE            0xff800000
 318 #ifdef CONFIG_PHYS_64BIT
 319 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 320 #else
 321 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 322 #endif
 323 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 324 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 325                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 326                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 327                                 | CSPR_V)
 328 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 329
 330 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 331                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 332                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 333                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 334                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 335                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 336                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 337
 338 #define CONFIG_SYS_NAND_ONFI_DETECTION
 339
 340 /* ONFI NAND Flash mode0 Timing Params */
 341 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 342                                         FTIM0_NAND_TWP(0x18)   | \
 343                                         FTIM0_NAND_TWCHT(0x07) | \
 344                                         FTIM0_NAND_TWH(0x0a))
 345 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 346                                         FTIM1_NAND_TWBE(0x39)  | \
 347                                         FTIM1_NAND_TRR(0x0e)   | \
 348                                         FTIM1_NAND_TRP(0x18))
 349 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 350                                         FTIM2_NAND_TREH(0x0a) | \
 351                                         FTIM2_NAND_TWHRE(0x1e))
 352 #define CONFIG_SYS_NAND_FTIM3           0x0
 353
 354 #define CONFIG_SYS_NAND_DDR_LAW         11
 355 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 356 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 357
 358 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 359
 360 #if defined(CONFIG_NAND)
 361 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 362 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 363 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 364 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 365 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 366 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 367 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 368 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 369 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 370 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 371 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 372 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 373 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 374 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 375 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 376 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 377 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 378 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 379 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 380 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 381 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 382 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 383 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 384 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 385 #else
 386 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 387 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 388 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 389 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 390 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 391 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 392 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 393 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 394 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 395 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 396 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 397 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 398 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 399 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 400 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 401 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 402 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 403 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 404 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 405 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 406 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 407 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 408 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 409 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 410 #endif
 411
 412 #ifdef CONFIG_SPL_BUILD
 413 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 414 #else
 415 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 416 #endif
 417
 418 #if defined(CONFIG_RAMBOOT_PBL)
 419 #define CONFIG_SYS_RAMBOOT
 420 #endif
 421
 422 #define CONFIG_MISC_INIT_R
 423
 424 #define CONFIG_HWCONFIG
 425
 426 /* define to use L1 as initial stack */
 427 #define CONFIG_L1_INIT_RAM
 428 #define CONFIG_SYS_INIT_RAM_LOCK
 429 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 430 #ifdef CONFIG_PHYS_64BIT
 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 433 /* The assembler doesn't like typecast */
 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 435         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 436           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 437 #else
 438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 441 #endif
 442 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 443
 444 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 445                                         GENERATED_GBL_DATA_SIZE)
 446 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 447
 448 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 449 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
 450
 451 /* Serial Port */
 452 #define CONFIG_SYS_NS16550_SERIAL
 453 #define CONFIG_SYS_NS16550_REG_SIZE     1
 454 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 455
 456 #define CONFIG_SYS_BAUDRATE_TABLE       \
 457         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 458
 459 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 460 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 461 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 462 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 463
 464 /* Video */
 465 #ifdef CONFIG_ARCH_T1024                /* no DIU on T1023 */
 466 #define CONFIG_FSL_DIU_FB
 467 #ifdef CONFIG_FSL_DIU_FB
 468 #define CONFIG_FSL_DIU_CH7301
 469 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
 470 #define CONFIG_VIDEO_LOGO
 471 #define CONFIG_VIDEO_BMP_LOGO
 472 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 473 /*
 474  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 475  * disable empty flash sector detection, which is I/O-intensive.
 476  */
 477 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 478 #endif
 479 #endif
 480
 481 /* I2C */
 482 #define CONFIG_SYS_I2C
 483 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 484 #define CONFIG_SYS_FSL_I2C_SPEED        50000   /* I2C speed in Hz */
 485 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 486 #define CONFIG_SYS_FSL_I2C2_SPEED       50000   /* I2C speed in Hz */
 487 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 488 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 489 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 490
 491 #define I2C_MUX_PCA_ADDR                0x77
 492 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 493 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 494 #define I2C_RETIMER_ADDR                0x18
 495
 496 /* I2C bus multiplexer */
 497 #define I2C_MUX_CH_DEFAULT      0x8
 498 #define I2C_MUX_CH_DIU          0xC
 499 #define I2C_MUX_CH5             0xD
 500 #define I2C_MUX_CH7             0xF
 501
 502 /* LDI/DVI Encoder for display */
 503 #define CONFIG_SYS_I2C_LDI_ADDR  0x38
 504 #define CONFIG_SYS_I2C_DVI_ADDR  0x75
 505
 506 /*
 507  * RTC configuration
 508  */
 509 #define RTC
 510 #define CONFIG_RTC_DS3231       1
 511 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 512
 513 /*
 514  * eSPI - Enhanced SPI
 515  */
 516 #define CONFIG_SPI_FLASH_BAR
 517 #define CONFIG_SF_DEFAULT_SPEED  10000000
 518 #define CONFIG_SF_DEFAULT_MODE    0
 519
 520 /*
 521  * General PCIe
 522  * Memory space is mapped 1-1, but I/O space must start from 0.
 523  */
 524 #define CONFIG_PCIE1            /* PCIE controller 1 */
 525 #define CONFIG_PCIE2            /* PCIE controller 2 */
 526 #define CONFIG_PCIE3            /* PCIE controller 3 */
 527 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 528 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 529 #define CONFIG_PCI_INDIRECT_BRIDGE
 530
 531 #ifdef CONFIG_PCI
 532 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 533 #ifdef CONFIG_PCIE1
 534 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 535 #ifdef CONFIG_PHYS_64BIT
 536 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 537 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 538 #else
 539 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 540 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 541 #endif
 542 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 543 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 544 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 545 #ifdef CONFIG_PHYS_64BIT
 546 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 547 #else
 548 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 549 #endif
 550 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 551 #endif
 552
 553 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 554 #ifdef CONFIG_PCIE2
 555 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
 556 #ifdef CONFIG_PHYS_64BIT
 557 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 558 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
 559 #else
 560 #define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 561 #define CONFIG_SYS_PCIE2_MEM_PHYS       0x90000000
 562 #endif
 563 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 564 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 565 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 566 #ifdef CONFIG_PHYS_64BIT
 567 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 568 #else
 569 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 570 #endif
 571 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 572 #endif
 573
 574 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 575 #ifdef CONFIG_PCIE3
 576 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 577 #ifdef CONFIG_PHYS_64BIT
 578 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 579 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 580 #else
 581 #define CONFIG_SYS_PCIE3_MEM_BUS        0xa0000000
 582 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xa0000000
 583 #endif
 584 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 585 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 586 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 587 #ifdef CONFIG_PHYS_64BIT
 588 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 589 #else
 590 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 591 #endif
 592 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 593 #endif
 594
 595 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 596 #endif  /* CONFIG_PCI */
 597
 598 /*
 599  *SATA
 600  */
 601 #define CONFIG_FSL_SATA_V2
 602 #ifdef CONFIG_FSL_SATA_V2
 603 #define CONFIG_SYS_SATA_MAX_DEVICE      1
 604 #define CONFIG_SATA1
 605 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 606 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 607 #define CONFIG_LBA48
 608 #endif
 609
 610 /*
 611  * USB
 612  */
 613 #define CONFIG_HAS_FSL_DR_USB
 614
 615 #ifdef CONFIG_HAS_FSL_DR_USB
 616 #define CONFIG_USB_EHCI_FSL
 617 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 618 #endif
 619
 620 /*
 621  * SDHC
 622  */
 623 #ifdef CONFIG_MMC
 624 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 625 #endif
 626
 627 /* Qman/Bman */
 628 #ifndef CONFIG_NOBQFMAN
 629 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 630 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 631 #ifdef CONFIG_PHYS_64BIT
 632 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 633 #else
 634 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 635 #endif
 636 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 637 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 638 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 639 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 640 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 641 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 642                                         CONFIG_SYS_BMAN_CENA_SIZE)
 643 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 644 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 645 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 646 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 647 #ifdef CONFIG_PHYS_64BIT
 648 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 649 #else
 650 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 651 #endif
 652 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 653 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 654 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 655 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 656 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 657 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 658                                         CONFIG_SYS_QMAN_CENA_SIZE)
 659 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 660 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 661
 662 #define CONFIG_SYS_DPAA_FMAN
 663
 664 #define CONFIG_QE
 665 #define CONFIG_U_QE
 666 /* Default address of microcode for the Linux FMan driver */
 667 #if defined(CONFIG_SPIFLASH)
 668 /*
 669  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 670  * env, so we got 0x110000.
 671  */
 672 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 673 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 674 #define CONFIG_SYS_QE_FW_ADDR   0x130000
 675 #elif defined(CONFIG_SDCARD)
 676 /*
 677  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 678  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 679  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
 680  */
 681 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 682 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 683 #define CONFIG_SYS_QE_FW_ADDR           (512 * 0x920)
 684 #elif defined(CONFIG_NAND)
 685 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 686 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 687 #define CONFIG_SYS_QE_FW_ADDR           (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 688 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 689 /*
 690  * Slave has no ucode locally, it can fetch this from remote. When implementing
 691  * in two corenet boards, slave's ucode could be stored in master's memory
 692  * space, the address can be mapped from slave TLB->slave LAW->
 693  * slave SRIO or PCIE outbound window->master inbound window->
 694  * master LAW->the ucode address in master's memory space.
 695  */
 696 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 697 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 698 #else
 699 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 700 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 701 #define CONFIG_SYS_QE_FW_ADDR           0xEFE00000
 702 #endif
 703 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 704 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 705 #endif /* CONFIG_NOBQFMAN */
 706
 707 #ifdef CONFIG_SYS_DPAA_FMAN
 708 #define CONFIG_FMAN_ENET
 709 #define CONFIG_PHYLIB_10G
 710 #define CONFIG_PHY_VITESSE
 711 #define CONFIG_PHY_REALTEK
 712 #define CONFIG_PHY_TERANETICS
 713 #define RGMII_PHY1_ADDR         0x1
 714 #define RGMII_PHY2_ADDR         0x2
 715 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
 716 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
 717 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
 718 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 719 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 720 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 721 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 722 #endif
 723
 724 #ifdef CONFIG_FMAN_ENET
 725 #define CONFIG_MII              /* MII PHY management */
 726 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 727 #endif
 728
 729 /*
 730  * Dynamic MTD Partition support with mtdparts
 731  */
 732 #ifdef CONFIG_MTD_NOR_FLASH
 733 #define CONFIG_FLASH_CFI_MTD
 734 #endif
 735
 736 /*
 737  * Environment
 738  */
 739 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 740 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 741
 742 /*
 743  * Miscellaneous configurable options
 744  */
 745 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 746
 747 /*
 748  * For booting Linux, the board info and command line data
 749  * have to be in the first 64 MB of memory, since this is
 750  * the maximum mapped by the Linux kernel during initialization.
 751  */
 752 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 753 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 754
 755 #ifdef CONFIG_CMD_KGDB
 756 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 757 #endif
 758
 759 /*
 760  * Environment Configuration
 761  */
 762 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 763 #define CONFIG_BOOTFILE         "uImage"
 764 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 765 #define CONFIG_LOADADDR         1000000 /* default location for tftp, bootm */
 766 #define __USB_PHY_TYPE          utmi
 767
 768 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 769         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
 770         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
 771         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
 772         "ramdiskfile=t1024qds/ramdisk.uboot\0"                  \
 773         "fdtfile=t1024qds/t1024qds.dtb\0"                       \
 774         "netdev=eth0\0"                                         \
 775         "video-mode=fslfb:1024x768-32@60,monitor=dvi\0"         \
 776         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 777         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 778         "tftpflash=tftpboot $loadaddr $uboot && "               \
 779         "protect off $ubootaddr +$filesize && "                 \
 780         "erase $ubootaddr +$filesize && "                       \
 781         "cp.b $loadaddr $ubootaddr $filesize && "               \
 782         "protect on $ubootaddr +$filesize && "                  \
 783         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 784         "consoledev=ttyS0\0"                                    \
 785         "ramdiskaddr=2000000\0"                                 \
 786         "fdtaddr=d00000\0"                                      \
 787         "bdev=sda3\0"
 788
 789 #define CONFIG_LINUX                                    \
 790         "setenv bootargs root=/dev/ram rw "             \
 791         "console=$consoledev,$baudrate $othbootargs;"   \
 792         "setenv ramdiskaddr 0x02000000;"                \
 793         "setenv fdtaddr 0x00c00000;"                    \
 794         "setenv loadaddr 0x1000000;"                    \
 795         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 796
 797 #define CONFIG_NFSBOOTCOMMAND                   \
 798         "setenv bootargs root=/dev/nfs rw "     \
 799         "nfsroot=$serverip:$rootpath "          \
 800         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 801         "console=$consoledev,$baudrate $othbootargs;"   \
 802         "tftp $loadaddr $bootfile;"             \
 803         "tftp $fdtaddr $fdtfile;"               \
 804         "bootm $loadaddr - $fdtaddr"
 805
 806 #define CONFIG_BOOTCOMMAND      CONFIG_LINUX
 807
 808 #include <asm/fsl_secure_boot.h>
 809
 810 #endif  /* __T1024QDS_H */