3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37 #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
38 #define CONFIG_SCM 1 /* ...on a System Controller Module */
39 #define CONFIG_CPM2 1 /* Has a CPM2 */
41 #define CONFIG_SYS_TEXT_BASE 0x40000000
43 #if (CONFIG_TQM8260 <= 100)
44 # error "TQM8260 module revison not supported"
47 /* We use a TQM8260 module with a 300MHz CPU */
50 /* Define 60x busmode only if your TQM8260 has L2 cache! */
51 #ifdef CONFIG_L2_CACHE
52 # define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
54 # undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
57 /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
59 # define CONFIG_BUSMODE_60x
62 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
64 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
68 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
70 #undef CONFIG_BOOTARGS
71 #define CONFIG_BOOTCOMMAND \
73 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
77 /* enable I2C and select the hardware/software driver */
78 #undef CONFIG_HARD_I2C /* I2C with hardware support */
79 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
80 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
81 #define CONFIG_SYS_I2C_SLAVE 0x7F
84 * Software (bit-bang) I2C driver configuration
87 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
88 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
89 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
90 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
91 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
92 else iop->pdat &= ~0x00010000
93 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
94 else iop->pdat &= ~0x00020000
95 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
97 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
98 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
99 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
100 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
105 * select serial console configuration
107 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
108 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
111 * if CONFIG_CONS_NONE is defined, then the serial console routines must
112 * defined elsewhere (for example, on the cogent platform, there are serial
113 * ports on the motherboard which are used for the serial console - see
114 * cogent/cma101/serial.[ch]).
116 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
117 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
118 #undef CONFIG_CONS_NONE /* define if console on something else*/
119 #ifdef CONFIG_82xx_CONS_SMC1
120 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
122 #ifdef CONFIG_82xx_CONS_SMC2
123 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
126 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
127 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
128 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
131 * select ethernet configuration
133 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
134 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
137 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
138 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
140 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
141 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
143 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
144 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
145 #undef CONFIG_ETHER_NONE /* define if ether on something else */
146 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
148 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
153 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
154 * - Enable Full Duplex in FSMR
156 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
157 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
158 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
159 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
161 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
166 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
167 * - Enable Full Duplex in FSMR
169 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
170 # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
171 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
172 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
174 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
177 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
178 #ifndef CONFIG_300MHz
179 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
181 #define CONFIG_8260_CLKIN 83333000 /* in Hz */
184 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
185 #define CONFIG_BAUDRATE 230400
187 #define CONFIG_BAUDRATE 115200
190 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
191 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
193 #undef CONFIG_WATCHDOG /* watchdog disabled */
198 #define CONFIG_BOOTP_SUBNETMASK
199 #define CONFIG_BOOTP_GATEWAY
200 #define CONFIG_BOOTP_HOSTNAME
201 #define CONFIG_BOOTP_BOOTPATH
202 #define CONFIG_BOOTP_BOOTFILESIZE
206 * Command line configuration.
208 #include <config_cmd_default.h>
210 #define CONFIG_CMD_DHCP
211 #define CONFIG_CMD_I2C
212 #define CONFIG_CMD_EEPROM
213 #define CONFIG_CMD_BSP
217 * Miscellaneous configurable options
219 #define CONFIG_SYS_LONGHELP /* undef to save memory */
220 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
221 #if defined(CONFIG_CMD_KGDB)
222 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
224 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
226 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
227 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
228 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
230 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
231 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
233 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
235 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
237 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
239 #define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
241 #define CONFIG_MISC_INIT_R /* have misc_init_r() function */
244 * For booting Linux, the board info and command line data
245 * have to be in the first 8 MB of memory, since this is
246 * the maximum mapped by the Linux kernel during initialization.
248 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
251 /* What should the base address of the main FLASH be and how big is
252 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
253 * The main FLASH is whichever is connected to *CS0.
255 #define CONFIG_SYS_FLASH0_BASE 0x40000000
256 #define CONFIG_SYS_FLASH1_BASE 0x60000000
257 #define CONFIG_SYS_FLASH0_SIZE 32
258 #define CONFIG_SYS_FLASH1_SIZE 32
260 /* Flash bank size (for preliminary settings)
262 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
264 /*-----------------------------------------------------------------------
267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
268 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
270 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
274 /* Start port with environment in flash; switch to EEPROM later */
275 #define CONFIG_ENV_IS_IN_FLASH 1
276 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000)
277 #define CONFIG_ENV_SIZE 0x40000
278 #define CONFIG_ENV_SECT_SIZE 0x40000
280 /* Final version: environment in EEPROM */
281 #define CONFIG_ENV_IS_IN_EEPROM 1
282 #define CONFIG_ENV_OFFSET 0
283 #define CONFIG_ENV_SIZE 2048
286 /*-----------------------------------------------------------------------
287 * Hardware Information Block
289 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
290 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
291 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
293 /*-----------------------------------------------------------------------
294 * Hard Reset Configuration Words
296 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
297 * defines for the various registers affected by the HRCW e.g. changing
298 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
300 #if defined(CONFIG_266MHz)
301 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
303 #elif defined(CONFIG_300MHz)
304 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
307 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
310 /* no slaves so just fill with zeros */
311 #define CONFIG_SYS_HRCW_SLAVE1 0
312 #define CONFIG_SYS_HRCW_SLAVE2 0
313 #define CONFIG_SYS_HRCW_SLAVE3 0
314 #define CONFIG_SYS_HRCW_SLAVE4 0
315 #define CONFIG_SYS_HRCW_SLAVE5 0
316 #define CONFIG_SYS_HRCW_SLAVE6 0
317 #define CONFIG_SYS_HRCW_SLAVE7 0
319 /*-----------------------------------------------------------------------
320 * Internal Memory Mapped Register
322 #define CONFIG_SYS_IMMR 0xFFF00000
324 /*-----------------------------------------------------------------------
325 * Definitions for initial stack pointer and data area (in DPRAM)
327 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
328 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
329 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
330 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
333 /*-----------------------------------------------------------------------
334 * Start addresses for the final memory configuration
335 * (Set up by the startup code)
336 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
338 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
339 * is mapped at SDRAM_BASE2_PRELIM.
341 #define CONFIG_SYS_SDRAM_BASE 0x00000000
342 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
343 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
344 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
345 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
348 * Internal Definitions
352 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
353 #define BOOTFLAG_WARM 0x02 /* Software reboot */
356 /*-----------------------------------------------------------------------
357 * Hardware Information Block
359 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
360 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
361 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
363 /*-----------------------------------------------------------------------
364 * Cache Configuration
366 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
367 #if defined(CONFIG_CMD_KGDB)
368 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
371 /*-----------------------------------------------------------------------
372 * HIDx - Hardware Implementation-dependent Registers 2-11
373 *-----------------------------------------------------------------------
374 * HID0 also contains cache control - initially enable both caches and
375 * invalidate contents, then the final state leaves only the instruction
376 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
377 * but Soft reset does not.
379 * HID1 has only read-only information - nothing to set.
381 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
383 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
384 #define CONFIG_SYS_HID2 0
386 /*-----------------------------------------------------------------------
387 * RMR - Reset Mode Register 5-5
388 *-----------------------------------------------------------------------
389 * turn on Checkstop Reset Enable
391 #define CONFIG_SYS_RMR RMR_CSRE
393 /*-----------------------------------------------------------------------
394 * BCR - Bus Configuration 4-25
395 *-----------------------------------------------------------------------
397 #ifdef CONFIG_BUSMODE_60x
398 #define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
399 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
401 #define BCR_APD01 0x10000000
402 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
405 /*-----------------------------------------------------------------------
406 * SIUMCR - SIU Module Configuration 4-31
407 *-----------------------------------------------------------------------
410 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
412 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
416 /*-----------------------------------------------------------------------
417 * SYPCR - System Protection Control 4-35
418 * SYPCR can only be written once after reset!
419 *-----------------------------------------------------------------------
420 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
422 #if defined(CONFIG_WATCHDOG)
423 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
424 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
426 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
427 SYPCR_SWRI|SYPCR_SWP)
428 #endif /* CONFIG_WATCHDOG */
430 /*-----------------------------------------------------------------------
431 * TMCNTSC - Time Counter Status and Control 4-40
432 *-----------------------------------------------------------------------
433 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
434 * and enable Time Counter
436 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
438 /*-----------------------------------------------------------------------
439 * PISCR - Periodic Interrupt Status and Control 4-42
440 *-----------------------------------------------------------------------
441 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
444 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
446 /*-----------------------------------------------------------------------
447 * SCCR - System Clock Control 9-8
448 *-----------------------------------------------------------------------
449 * Ensure DFBRG is Divide by 16
451 #define CONFIG_SYS_SCCR 0
453 /*-----------------------------------------------------------------------
454 * RCCR - RISC Controller Configuration 13-7
455 *-----------------------------------------------------------------------
457 #define CONFIG_SYS_RCCR 0
460 * Init Memory Controller:
462 * Bank Bus Machine PortSz Device
463 * ---- --- ------- ------ ------
464 * 0 60x GPCM 64 bit FLASH
465 * 1 60x SDRAM 64 bit SDRAM
466 * 2 Local SDRAM 32 bit SDRAM
470 /* Initialize SDRAM on local bus
472 #define CONFIG_SYS_INIT_LOCAL_SDRAM
474 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
476 /* Minimum mask to separate preliminary
477 * address ranges for CS[0:2]
479 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
480 #define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
482 #define CONFIG_SYS_MPTPR 0x4000
484 /*-----------------------------------------------------------------------------
485 * Address for Mode Register Set (MRS) command
486 *-----------------------------------------------------------------------------
487 * In fact, the address is rather configuration data presented to the SDRAM on
488 * its address lines. Because the address lines may be mux'ed externally either
489 * for 8 column or 9 column devices, some bits appear twice in the 8260's
492 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
493 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
494 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
495 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
496 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
497 *-----------------------------------------------------------------------------
499 #define CONFIG_SYS_MRS_OFFS 0x00000110
504 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
509 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
516 /* SDRAM on TQM8260 can have either 8 or 9 columns.
517 * The number affects configuration values.
520 /* Bank 1 - 60x bus SDRAM
522 #define CONFIG_SYS_PSRT 0x20
523 #define CONFIG_SYS_LSRT 0x20
524 #ifndef CONFIG_SYS_RAMBOOT
525 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
530 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
533 /* SDRAM initialization values for 8-column chips
535 #define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
537 ORxS_ROWST_PBI1_A7 |\
540 #define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
541 PSDMR_SDAM_A15_IS_A5 |\
542 PSDMR_BSMA_A12_A14 |\
543 PSDMR_SDA10_PBI1_A8 |\
552 /* SDRAM initialization values for 9-column chips
554 #define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
556 ORxS_ROWST_PBI1_A5 |\
559 #define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
560 PSDMR_SDAM_A16_IS_A5 |\
561 PSDMR_BSMA_A12_A14 |\
562 PSDMR_SDA10_PBI1_A7 |\
571 /* Bank 2 - Local bus SDRAM
573 #ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
574 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
579 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
581 #define SDRAM_BASE2_PRELIM 0x80000000
583 /* SDRAM initialization values for 8-column chips
585 #define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
587 ORxS_ROWST_PBI1_A8 |\
590 #define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\
591 PSDMR_SDAM_A15_IS_A5 |\
592 PSDMR_BSMA_A13_A15 |\
593 PSDMR_SDA10_PBI1_A9 |\
602 /* SDRAM initialization values for 9-column chips
604 #define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
606 ORxS_ROWST_PBI1_A6 |\
609 #define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
610 PSDMR_SDAM_A16_IS_A5 |\
611 PSDMR_BSMA_A13_A15 |\
612 PSDMR_SDA10_PBI1_A8 |\
621 #endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
623 #endif /* CONFIG_SYS_RAMBOOT */
625 #define CONFIG_SYS_CAN0_BASE 0xc0000000
626 #define CONFIG_SYS_CAN1_BASE 0xc0008000
627 #define CONFIG_SYS_FIOX_BASE 0xc0010000
628 #define CONFIG_SYS_FDOHM_BASE 0xc0018000
629 #define CONFIG_SYS_EXTPROM_BASE 0xc2000000
631 #define CONFIG_SYS_CAN_SIZE 0x00000100
632 #define CONFIG_SYS_FIOX_SIZE 0x00000020
633 #define CONFIG_SYS_FDOHM_SIZE 0x00002000
634 #define CONFIG_SYS_EXTPROM_BANK_SIZE 0x01000000
636 #define EXT_EEPROM_MAX_FLASH_BANKS 0x02
640 #define CONFIG_SYS_CAN0_BR3 ((CONFIG_SYS_CAN0_BASE & BRx_BA_MSK) |\
645 #define CONFIG_SYS_CAN0_OR3 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\
651 #define CONFIG_SYS_CAN1_BR4 ((CONFIG_SYS_CAN1_BASE & BRx_BA_MSK) |\
656 #define CONFIG_SYS_CAN1_OR4 (P2SZ_TO_AM(CONFIG_SYS_CAN_SIZE) |\
660 /* CS5 - Extended PROM (16MB optional)
662 #define CONFIG_SYS_EXTPROM_BR5 ((CONFIG_SYS_EXTPROM_BASE & BRx_BA_MSK)|\
667 #define CONFIG_SYS_EXTPROM_OR5 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
673 /* CS6 - Extended PROM (16MB optional)
675 #define CONFIG_SYS_EXTPROM_BR6 (((CONFIG_SYS_EXTPROM_BASE + \
676 CONFIG_SYS_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
681 #define CONFIG_SYS_EXTPROM_OR6 (P2SZ_TO_AM(CONFIG_SYS_EXTPROM_BANK_SIZE)|\
687 /* CS7 - FPGA FIOX: Glue Logic
689 #define CONFIG_SYS_FIOX_BR7 ((CONFIG_SYS_FIOX_BASE & BRx_BA_MSK) |\
694 #define CONFIG_SYS_FIOX_OR7 (P2SZ_TO_AM(CONFIG_SYS_FIOX_SIZE) |\
699 /* CS8 - FPGA DOH Master
701 #define CONFIG_SYS_FDOHM_BR8 ((CONFIG_SYS_FDOHM_BASE & BRx_BA_MSK) |\
706 #define CONFIG_SYS_FDOHM_OR8 (P2SZ_TO_AM(CONFIG_SYS_FDOHM_SIZE) |\
712 /* FPGA configuration */
713 #define CONFIG_SYS_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */
714 #define CONFIG_SYS_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */
715 #define CONFIG_SYS_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */
717 #define CONFIG_SYS_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
718 #define CONFIG_SYS_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */
719 #define CONFIG_SYS_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */
722 #endif /* __CONFIG_H */