2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Analogue&Micro Rattler boards.
7 * SPDX-License-Identifier: GPL-2.0+
14 #define CPU_ID_STR "MPC8248"
16 #define CPU_ID_STR "MPC8250"
17 #endif /* CONFIG_MPC8248 */
19 #define CONFIG_SYS_TEXT_BASE 0xFE000000
21 #define CONFIG_CPM2 1 /* Has a CPM2 */
23 #define CONFIG_RATTLER /* Analogue&Micro Rattler board */
25 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
26 #define CONFIG_ENV_OVERWRITE
29 * Select serial console configuration
31 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
32 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
35 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
36 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
37 #undef CONFIG_CONS_NONE /* It's not on external UART */
38 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
41 * Select ethernet configuration
43 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
44 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
47 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
48 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
51 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
52 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
53 #undef CONFIG_ETHER_NONE /* No external Ethernet */
55 #ifdef CONFIG_ETHER_ON_FCC
57 #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
59 #if (CONFIG_ETHER_INDEX == 1)
61 /* - Rx clock is CLK11
63 * - BDs/buffers on 60x bus
66 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
67 #define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
68 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
69 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
71 #elif (CONFIG_ETHER_INDEX == 2)
73 /* - Rx clock is CLK15
75 * - BDs/buffers on 60x bus
78 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
79 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
80 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
81 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
83 #endif /* CONFIG_ETHER_INDEX */
85 #define CONFIG_MII /* MII PHY management */
86 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
88 * GPIO pins used for bit-banged MII communications
90 #define MDIO_PORT 2 /* Port C */
91 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
92 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
93 #define MDC_DECLARE MDIO_DECLARE
95 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
96 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
97 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
99 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
100 else iop->pdat &= ~0x00400000
102 #define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
103 else iop->pdat &= ~0x00800000
105 #define MIIDELAY udelay(1)
107 #endif /* CONFIG_ETHER_ON_FCC */
109 #ifndef CONFIG_8260_CLKIN
110 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
113 #define CONFIG_BAUDRATE 38400
119 #define CONFIG_BOOTP_BOOTFILESIZE
120 #define CONFIG_BOOTP_BOOTPATH
121 #define CONFIG_BOOTP_GATEWAY
122 #define CONFIG_BOOTP_HOSTNAME
126 * Command line configuration.
128 #include <config_cmd_default.h>
130 #define CONFIG_CMD_DHCP
131 #define CONFIG_CMD_IMMAP
132 #define CONFIG_CMD_JFFS2
133 #define CONFIG_CMD_MII
134 #define CONFIG_CMD_PING
137 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
138 #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
139 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
141 #if defined(CONFIG_CMD_KGDB)
142 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
143 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
144 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
145 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
146 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
149 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
150 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
153 * Miscellaneous configurable options
155 #define CONFIG_SYS_HUSH_PARSER
156 #define CONFIG_SYS_LONGHELP /* undef to save memory */
157 #if defined(CONFIG_CMD_KGDB)
158 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
160 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
163 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
164 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
166 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
167 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
169 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
171 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
173 #define CONFIG_SYS_FLASH_BASE 0xFE000000
174 #define CONFIG_SYS_FLASH_CFI
175 #define CONFIG_FLASH_CFI_DRIVER
176 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
177 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
179 #define CONFIG_SYS_DIRECT_FLASH_TFTP
181 #if defined(CONFIG_CMD_JFFS2)
182 #define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
183 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
189 /* No command line, one static partition */
190 #undef CONFIG_CMD_MTDPARTS
191 #define CONFIG_JFFS2_DEV "nor0"
192 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
193 #define CONFIG_JFFS2_PART_OFFSET 0x00100000
195 /* mtdparts command line support */
196 /* Note: fake mtd_id used, no linux mtd map file */
198 #define CONFIG_CMD_MTDPARTS
199 #define MTDIDS_DEFAULT "nor0=rattler-0"
200 #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
202 #endif /* CONFIG_CMD_JFFS2 */
204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
205 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
206 #define CONFIG_SYS_RAMBOOT
209 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
211 #define CONFIG_ENV_IS_IN_FLASH
213 #ifdef CONFIG_ENV_IS_IN_FLASH
214 #define CONFIG_ENV_SECT_SIZE 0x10000
215 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
216 #endif /* CONFIG_ENV_IS_IN_FLASH */
218 #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
220 #define CONFIG_SYS_IMMR 0xF0000000
222 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
223 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
224 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
227 #define CONFIG_SYS_SDRAM_BASE 0x00000000
228 #define CONFIG_SYS_SDRAM_SIZE 32
229 #define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
230 #define CONFIG_SYS_SDRAM_OR 0xFE002EC0
232 #define CONFIG_SYS_BCSR 0xFC000000
234 /* Hard reset configuration word */
235 #define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
237 #define CONFIG_SYS_HRCW_SLAVE1 0
238 #define CONFIG_SYS_HRCW_SLAVE2 0
239 #define CONFIG_SYS_HRCW_SLAVE3 0
240 #define CONFIG_SYS_HRCW_SLAVE4 0
241 #define CONFIG_SYS_HRCW_SLAVE5 0
242 #define CONFIG_SYS_HRCW_SLAVE6 0
243 #define CONFIG_SYS_HRCW_SLAVE7 0
245 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
246 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
248 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
249 #if defined(CONFIG_CMD_KGDB)
250 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
253 #define CONFIG_SYS_HID0_INIT 0
254 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
256 #define CONFIG_SYS_HID2 0
258 #define CONFIG_SYS_SIUMCR 0x0E04C000
259 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
260 #define CONFIG_SYS_BCR 0x00000000
261 #define CONFIG_SYS_SCCR SCCR_DFBRG01
263 #define CONFIG_SYS_RMR RMR_CSRE
264 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
265 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
266 #define CONFIG_SYS_RCCR 0
268 #define CONFIG_SYS_PSDMR 0x8249A452
269 #define CONFIG_SYS_PSRT 0x1F
270 #define CONFIG_SYS_MPTPR 0x2000
272 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
273 #define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
274 #define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
275 #define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
277 #define CONFIG_SYS_RESET_ADDRESS 0xC0000000
279 #endif /* __CONFIG_H */