2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
35 * High Level Configuration Options
39 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40 #define CONFIG_RBC823 1 /* ...on a RBC823 module */
42 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
46 #define CONFIG_LAST_STAGE_INIT
48 #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
49 #define CONFIG_LCD 1 /* use LCD controller ... */
50 #define CONFIG_MPC8XX_LCD
51 #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
53 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
54 #undef CONFIG_8xx_CONS_SMC1
55 #undef CONFIG_8xx_CONS_NONE
56 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
58 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
63 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
64 #define CONFIG_8xx_GCLK_FREQ 48000000L
66 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
68 #undef CONFIG_BOOTARGS
69 #define CONFIG_BOOTCOMMAND \
71 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
72 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
75 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
76 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
78 #undef CONFIG_WATCHDOG /* watchdog disabled */
80 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
82 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
87 #define CONFIG_BOOTP_SUBNETMASK
88 #define CONFIG_BOOTP_GATEWAY
89 #define CONFIG_BOOTP_HOSTNAME
90 #define CONFIG_BOOTP_BOOTPATH
91 #define CONFIG_BOOTP_BOOTFILESIZE
94 #undef CONFIG_MAC_PARTITION
95 #define CONFIG_DOS_PARTITION
97 #undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
99 #define CONFIG_HARD_I2C
100 #define CONFIG_SYS_I2C_SPEED 40000
101 #define CONFIG_SYS_I2C_SLAVE 0xfe
102 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
104 #define CONFIG_SYS_EEPROM_WRITE_BITS 4
105 #define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
108 * Command line configuration.
110 #include <config_cmd_default.h>
112 #define CONFIG_CMD_ASKENV
113 #define CONFIG_CMD_BEDBUG
114 #define CONFIG_CMD_BMP
115 #define CONFIG_CMD_CACHE
116 #define CONFIG_CMD_CDP
117 #define CONFIG_CMD_DHCP
118 #define CONFIG_CMD_DIAG
119 #define CONFIG_CMD_EEPROM
120 #define CONFIG_CMD_ELF
121 #define CONFIG_CMD_FAT
122 #define CONFIG_CMD_I2C
123 #define CONFIG_CMD_IMMAP
124 #define CONFIG_CMD_KGDB
125 #define CONFIG_CMD_PING
126 #define CONFIG_CMD_PORTIO
127 #define CONFIG_CMD_REGINFO
128 #define CONFIG_CMD_SAVES
129 #define CONFIG_CMD_SDRAM
131 #undef CONFIG_CMD_SETGETDCR
132 #undef CONFIG_CMD_XIMG
135 * Miscellaneous configurable options
137 #define CONFIG_SYS_LONGHELP /* undef to save memory */
138 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
139 #if defined(CONFIG_CMD_KGDB)
140 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
142 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
148 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
151 #define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
153 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
160 /*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
163 #define CONFIG_SYS_IMMR 0xFF000000
165 /*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
168 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
169 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
173 /*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration
175 * (Set up by the startup code)
176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
178 #define CONFIG_SYS_SDRAM_BASE 0x00000000
179 #define CONFIG_SYS_FLASH_BASE 0xFFF00000
181 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
183 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
193 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195 /*-----------------------------------------------------------------------
198 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
199 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
201 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
204 #define CONFIG_ENV_IS_IN_FLASH 1
205 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
206 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
208 /*-----------------------------------------------------------------------
209 * Cache Configuration
211 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
212 #if defined(CONFIG_CMD_KGDB)
213 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216 /*-----------------------------------------------------------------------
217 * SYPCR - System Protection Control 11-9
218 * SYPCR can only be written once after reset!
219 *-----------------------------------------------------------------------
220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
222 #if defined(CONFIG_WATCHDOG)
223 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
224 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
227 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
229 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
232 /*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
235 * PCMCIA config., multi-function pin tri-state
237 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
239 /*-----------------------------------------------------------------------
240 * TBSCR - Time Base Status and Control 11-26
241 *-----------------------------------------------------------------------
242 * Clear Reference Interrupt Status, Timebase freezing enabled
244 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
246 /*-----------------------------------------------------------------------
247 * RTCSC - Real-Time Clock Status and Control Register 11-27
248 *-----------------------------------------------------------------------
250 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
252 /*-----------------------------------------------------------------------
253 * PISCR - Periodic Interrupt Status and Control 11-31
254 *-----------------------------------------------------------------------
255 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
257 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
259 /*-----------------------------------------------------------------------
260 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
261 *-----------------------------------------------------------------------
262 * Reset PLL lock status sticky bit, timer expired status bit and timer
263 * interrupt status bit
268 * for 48 MHz, we use a 4 MHz clock * 12
270 #define CONFIG_SYS_PLPRCR \
271 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
273 /*-----------------------------------------------------------------------
274 * SCCR - System Clock and reset Control Register 15-27
275 *-----------------------------------------------------------------------
276 * Set clock output, timebase and RTC source and divider,
277 * power management and some other internal clocks
279 #define SCCR_MASK SCCR_EBDF11
280 #define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
281 SCCR_PRQEN | SCCR_EBDF00 | \
282 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
283 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
287 /*-----------------------------------------------------------------------
289 *-----------------------------------------------------------------------
292 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
293 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
294 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
295 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
296 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
297 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
298 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
299 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
301 /*-----------------------------------------------------------------------
302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303 *-----------------------------------------------------------------------
306 #define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
308 #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
309 #undef CONFIG_IDE_LED /* LED for ide not supported */
310 #undef CONFIG_IDE_RESET /* reset for ide not supported */
312 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
313 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
315 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
317 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
319 /* Offset for data I/O */
320 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
322 /* Offset for normal register accesses */
323 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
325 /* Offset for alternate registers */
326 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
330 /*-----------------------------------------------------------------------
332 *-----------------------------------------------------------------------
335 /*#define CONFIG_SYS_DER 0x2002000F*/
336 #define CONFIG_SYS_DER 0
339 * Init Memory Controller:
341 * BR0/1 and OR0/1 (FLASH)
344 #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
345 #define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
347 /* used to re-map FLASH both when starting from SRAM or FLASH:
348 * restrict access enough to keep SRAM working (if any)
349 * but not too much to meddle with FLASH accesses
351 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
353 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
354 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
356 #define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
358 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
359 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
361 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
362 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
366 * BR4 and OR4 (SDRAM)
369 #define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
370 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
375 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
377 #define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
378 #define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
381 * Memory Periodic Timer Prescaler
384 /* periodic timer for refresh */
385 #define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
387 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
388 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
389 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
391 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
392 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
393 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
396 * MAMR settings for SDRAM
400 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
401 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
402 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
404 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
405 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
406 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
412 /* No command line, one static partition, whole device */
413 #undef CONFIG_CMD_MTDPARTS
414 #define CONFIG_JFFS2_DEV "nor0"
415 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
416 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
418 /* mtdparts command line support */
419 /* Note: fake mtd_id used, no linux mtd map file */
421 #define CONFIG_CMD_MTDPARTS
422 #define MTDIDS_DEFAULT ""
423 #define MTDPARTS_DEFAULT ""
426 #endif /* __CONFIG_H */