2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
35 * High Level Configuration Options
39 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40 #define CONFIG_RBC823 1 /* ...on a RBC823 module */
45 #define CONFIG_LAST_STAGE_INIT
47 #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
48 #define CONFIG_LCD 1 /* use LCD controller ... */
49 #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
51 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
52 #undef CONFIG_8xx_CONS_SMC1
53 #undef CONFIG_8xx_CONS_NONE
54 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
62 #define CONFIG_8xx_GCLK_FREQ 48000000L
64 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
66 #undef CONFIG_BOOTARGS
67 #define CONFIG_BOOTCOMMAND \
69 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
70 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
73 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
76 #undef CONFIG_WATCHDOG /* watchdog disabled */
78 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
80 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
82 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
84 #undef CONFIG_MAC_PARTITION
85 #define CONFIG_DOS_PARTITION
87 #undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
89 #define CONFIG_HARD_I2C
90 #define CFG_I2C_SPEED 40000
91 #define CFG_I2C_SLAVE 0xfe
92 #define CFG_I2C_EEPROM_ADDR 0x50
93 #define CFG_I2C_EEPROM_ADDR_LEN 1
94 #define CFG_EEPROM_WRITE_BITS 4
95 #define CFG_EEPROM_WRITE_DELAY_MS 10
97 #define CONFIG_COMMANDS ( CFG_CMD_ALL & \
114 ~CFG_CMD_SETGETDCR & \
120 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
121 #include <cmd_confdefs.h>
124 * Miscellaneous configurable options
126 #define CFG_LONGHELP /* undef to save memory */
127 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
128 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
129 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
131 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
133 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
134 #define CFG_MAXARGS 16 /* max number of command args */
135 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
137 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
138 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
140 #define CFG_LOAD_ADDR 0x0100000 /* default load address */
142 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
144 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
147 * Low Level Configuration Settings
148 * (address mappings, register initial values, etc.)
149 * You should know what you are doing if you make changes here.
151 /*-----------------------------------------------------------------------
152 * Internal Memory Mapped Register
154 #define CFG_IMMR 0xFF000000
156 /*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
159 #define CFG_INIT_RAM_ADDR CFG_IMMR
160 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
161 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
162 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165 /*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 #define CFG_SDRAM_BASE 0x00000000
171 #define CFG_FLASH_BASE 0xFFF00000
173 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
175 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
177 #define CFG_MONITOR_BASE CFG_FLASH_BASE
178 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
185 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
187 /*-----------------------------------------------------------------------
190 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
191 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
193 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
196 #define CFG_ENV_IS_IN_FLASH 1
197 #define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
198 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
200 /*-----------------------------------------------------------------------
201 * Cache Configuration
203 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
204 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
205 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
208 /*-----------------------------------------------------------------------
209 * SYPCR - System Protection Control 11-9
210 * SYPCR can only be written once after reset!
211 *-----------------------------------------------------------------------
212 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
214 #if defined(CONFIG_WATCHDOG)
215 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
216 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
219 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
221 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
224 /*-----------------------------------------------------------------------
225 * SIUMCR - SIU Module Configuration 11-6
226 *-----------------------------------------------------------------------
227 * PCMCIA config., multi-function pin tri-state
229 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
231 /*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
236 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
238 /*-----------------------------------------------------------------------
239 * RTCSC - Real-Time Clock Status and Control Register 11-27
240 *-----------------------------------------------------------------------
242 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
244 /*-----------------------------------------------------------------------
245 * PISCR - Periodic Interrupt Status and Control 11-31
246 *-----------------------------------------------------------------------
247 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
249 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
251 /*-----------------------------------------------------------------------
252 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
253 *-----------------------------------------------------------------------
254 * Reset PLL lock status sticky bit, timer expired status bit and timer
255 * interrupt status bit
260 * for 48 MHz, we use a 4 MHz clock * 12
263 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
265 /*-----------------------------------------------------------------------
266 * SCCR - System Clock and reset Control Register 15-27
267 *-----------------------------------------------------------------------
268 * Set clock output, timebase and RTC source and divider,
269 * power management and some other internal clocks
271 #define SCCR_MASK SCCR_EBDF11
272 #define CFG_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
273 SCCR_PRQEN | SCCR_EBDF00 | \
274 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
279 /*-----------------------------------------------------------------------
281 *-----------------------------------------------------------------------
284 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
285 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
286 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
287 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
288 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
289 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
290 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
291 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
293 /*-----------------------------------------------------------------------
294 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
295 *-----------------------------------------------------------------------
298 #define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
300 #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
301 #undef CONFIG_IDE_LED /* LED for ide not supported */
302 #undef CONFIG_IDE_RESET /* reset for ide not supported */
304 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
305 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
307 #define CFG_ATA_IDE0_OFFSET 0x0000
309 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
311 /* Offset for data I/O */
312 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
314 /* Offset for normal register accesses */
315 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
317 /* Offset for alternate registers */
318 #define CFG_ATA_ALT_OFFSET 0x0100
322 /************************************************************
323 * Disk-On-Chip configuration
324 ************************************************************/
325 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
326 #define CFG_DOC_SHORT_TIMEOUT
327 #define CFG_DOC_SUPPORT_2000
328 #define CFG_DOC_SUPPORT_MILLENNIUM
330 /*-----------------------------------------------------------------------
332 *-----------------------------------------------------------------------
335 /*#define CFG_DER 0x2002000F*/
339 * Init Memory Controller:
341 * BR0/1 and OR0/1 (FLASH)
344 #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
345 #define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
347 /* used to re-map FLASH both when starting from SRAM or FLASH:
348 * restrict access enough to keep SRAM working (if any)
349 * but not too much to meddle with FLASH accesses
351 #define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
353 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
354 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
356 #define CFG_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
358 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
359 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
361 #define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
362 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
366 * BR4 and OR4 (SDRAM)
369 #define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
370 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
375 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM)
377 #define CFG_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
378 #define CFG_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
381 * Memory Periodic Timer Prescaler
384 /* periodic timer for refresh */
385 #define CFG_MAMR_PTA 187 /* start with divider for 48 MHz */
387 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
388 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
389 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
391 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
392 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
393 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
396 * MAMR settings for SDRAM
400 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
401 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
402 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
404 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
405 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
406 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
410 * Internal Definitions
414 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
415 #define BOOTFLAG_WARM 0x02 /* Software reboot */
417 #endif /* __CONFIG_H */