2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
21 #define CONFIG_PLU405 1 /* ...on a PLU405 board */
23 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
25 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
27 #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
29 #undef CONFIG_BOOTARGS
30 #undef CONFIG_BOOTCOMMAND
32 #define CONFIG_PREBOOT /* enable preboot variable */
34 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
36 #undef CONFIG_HAS_ETH1
38 #define CONFIG_PPC4xx_EMAC
39 #define CONFIG_MII 1 /* MII PHY management */
40 #define CONFIG_PHY_ADDR 0 /* PHY address */
41 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
42 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
44 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
49 #define CONFIG_BOOTP_BOOTFILESIZE
50 #define CONFIG_BOOTP_BOOTPATH
51 #define CONFIG_BOOTP_GATEWAY
52 #define CONFIG_BOOTP_HOSTNAME
55 * Command line configuration.
57 #define CONFIG_CMD_PCI
58 #define CONFIG_CMD_IRQ
59 #define CONFIG_CMD_IDE
60 #define CONFIG_CMD_NAND
61 #define CONFIG_CMD_DATE
62 #define CONFIG_CMD_EEPROM
64 #define CONFIG_SUPPORT_VFAT
66 #undef CONFIG_WATCHDOG /* watchdog disabled */
68 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
69 #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
71 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
74 * Miscellaneous configurable options
76 #define CONFIG_SYS_LONGHELP /* undef to save memory */
78 #if defined(CONFIG_CMD_KGDB)
79 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
81 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
84 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
85 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
87 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
89 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
91 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
92 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
94 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
95 #define CONFIG_SYS_NS16550_SERIAL
96 #define CONFIG_SYS_NS16550_REG_SIZE 1
97 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
99 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
100 #define CONFIG_SYS_BASE_BAUD 691200
102 /* The following table includes the supported baudrates */
103 #define CONFIG_SYS_BAUDRATE_TABLE \
104 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
105 57600, 115200, 230400, 460800, 921600 }
107 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
108 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
110 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
112 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
117 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
119 #define NAND_BIG_DELAY_US 25
121 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
122 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
123 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
124 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
126 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
127 #define CONFIG_SYS_NAND_QUIET 1
132 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
133 #define PCI_HOST_FORCE 1 /* configure as pci host */
134 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
136 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
137 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
138 /* resource configuration */
140 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
142 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
144 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
145 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
146 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
147 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
148 #define CONFIG_SYS_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
149 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
150 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
151 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
152 #define CONFIG_SYS_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
157 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
158 #undef CONFIG_IDE_LED /* no led for ide supported */
159 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
161 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
162 /* max. 1 drives per IDE bus */
163 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
165 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
166 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
168 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
169 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
170 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
173 * For booting Linux, the board info and command line data
174 * have to be in the first 8 MB of memory, since this is
175 * the maximum mapped by the Linux kernel during initialization.
177 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
190 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
191 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
192 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
194 * The following defines are added for buggy IOP480 byte interface.
195 * All other boards should use the standard values (CPCI405 etc.)
197 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
198 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
199 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
201 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
208 #define CONFIG_SYS_SDRAM_BASE 0x00000000
209 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
211 #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
212 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
215 * Environment Variable setup
217 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
218 #define CONFIG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
219 #define CONFIG_ENV_SIZE 0x700
222 * I2C EEPROM (24WC16) for environment
224 #define CONFIG_SYS_I2C
225 #define CONFIG_SYS_I2C_PPC4XX
226 #define CONFIG_SYS_I2C_PPC4XX_CH0
227 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
228 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
230 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
231 #define CONFIG_SYS_EEPROM_WREN 1
234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
235 /* mask of address bits that overflow into the "EEPROM chip address" */
236 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
238 /* 16 byte page write mode using */
239 /* last 4 bits of the address */
240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
243 * External Bus Controller (EBC) Setup
245 #define CAN0_BA 0xF0000000 /* CAN0 Base Address */
246 #define CAN1_BA 0xF0000100 /* CAN1 Base Address */
247 #define DUART0_BA 0xF0000400 /* DUART Base Address */
248 #define DUART1_BA 0xF0000408 /* DUART Base Address */
249 #define RTC_BA 0xF0000500 /* RTC Base Address */
250 #define VGA_BA 0xF1000000 /* Epson VGA Base Address */
251 #define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
253 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
254 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
255 #define CONFIG_SYS_EBC_PB0AP 0x92015480
256 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
257 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
259 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
260 #define CONFIG_SYS_EBC_PB1AP 0x92015480
261 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
262 #define CONFIG_SYS_EBC_PB1CR 0xF4018000
264 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
265 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
266 #define CONFIG_SYS_EBC_PB2AP 0x010053C0
267 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
268 #define CONFIG_SYS_EBC_PB2CR 0xF0018000
270 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
271 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272 #define CONFIG_SYS_EBC_PB3AP 0x010053C0
273 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
274 #define CONFIG_SYS_EBC_PB3CR 0xF011A000
279 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
281 /* FPGA internal regs */
282 #define CONFIG_SYS_FPGA_CTRL 0x000
284 /* FPGA Control Reg */
285 #define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
286 #define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
287 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
289 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
290 #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
292 /* FPGA program pin configuration */
293 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
294 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
295 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
296 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
297 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
300 * Definitions for initial stack pointer and data area (in data cache)
302 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
303 #define CONFIG_SYS_TEMP_STACK_OCM 1
305 /* On Chip Memory location */
306 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
307 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
308 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
309 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
312 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315 * Definitions for GPIO setup (PPC405EP specific)
317 * GPIO0[0] - External Bus Controller BLAST output
318 * GPIO0[1-9] - Instruction trace outputs -> GPIO
319 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
320 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
321 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
322 * GPIO0[24-27] - UART0 control signal inputs/outputs
323 * GPIO0[28-29] - UART1 data signal input/output
324 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
326 #define CONFIG_SYS_GPIO0_OSRL 0x00000550
327 #define CONFIG_SYS_GPIO0_OSRH 0x00000110
328 #define CONFIG_SYS_GPIO0_ISR1L 0x00000000
329 #define CONFIG_SYS_GPIO0_ISR1H 0x15555445
330 #define CONFIG_SYS_GPIO0_TSRL 0x00000000
331 #define CONFIG_SYS_GPIO0_TSRH 0x00000000
332 #define CONFIG_SYS_GPIO0_TCR 0x77FE0014
334 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
335 #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
338 * Default speed selection (cpu_plb_opb_ebc) in MHz.
339 * This value will be set if iic boot eprom is disabled.
342 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
343 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
346 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
347 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
350 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
351 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
355 * PCI OHCI controller
357 #define CONFIG_USB_OHCI_NEW 1
358 #define CONFIG_PCI_OHCI 1
359 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
360 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
361 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
366 #define CONFIG_RBTREE
367 #define CONFIG_MTD_DEVICE
368 #define CONFIG_MTD_PARTITIONS
369 #define CONFIG_CMD_MTDPARTS
372 #endif /* __CONFIG_H */