3 * Denis Peter d.peter@mpl.ch
5 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
19 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
20 #define CONFIG_PATI 1 /* ...On a PATI board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
24 /* Serial Console Configuration */
25 #define CONFIG_5xx_CONS_SCI1
26 #undef CONFIG_5xx_CONS_SCI2
28 #define CONFIG_BAUDRATE 9600
33 #define CONFIG_BOOTP_BOOTFILESIZE
34 #define CONFIG_BOOTP_BOOTPATH
35 #define CONFIG_BOOTP_GATEWAY
36 #define CONFIG_BOOTP_HOSTNAME
39 * Command line configuration.
41 #define CONFIG_CMD_REGINFO
42 #define CONFIG_CMD_REGINFO
43 #define CONFIG_CMD_BSP
44 #define CONFIG_CMD_EEPROM
45 #define CONFIG_CMD_IRQ
47 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
49 #define CONFIG_BOOTARGS "" /* */
51 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
53 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
56 * Miscellaneous configurable options
58 #define CONFIG_PREBOOT
60 #define CONFIG_SYS_LONGHELP /* undef to save memory */
61 #if defined(CONFIG_CMD_KGDB)
62 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
64 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
66 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
67 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
68 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
70 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
71 #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
73 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
75 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
77 #define CONFIG_BOARD_EARLY_INIT_F
79 /***********************************************************************
81 ***********************************************************************/
82 #define CONFIG_LAST_STAGE_INIT
85 * Low Level Configuration Settings
89 * Internal Memory Mapped (This is not the IMMR content)
91 #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
94 * Definitions for initial stack pointer and data area
96 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
97 #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
98 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
99 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
101 * Start addresses for the final memory configuration
102 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
104 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
105 #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
106 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */
107 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
108 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
110 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
111 /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
112 /* This adress is given to the linker with -Ttext to */
113 /* locate the text section at this adress. */
114 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
115 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
117 #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
120 * For booting Linux, the board info and command line data
121 * have to be in the first 8 MB of memory, since this is
122 * the maximum mapped by the Linux kernel during initialization.
124 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
126 /*-----------------------------------------------------------------------
128 *-----------------------------------------------------------------------
132 #define CONFIG_SYS_FLASH_PROTECTION
133 #define CONFIG_SYS_FLASH_EMPTY_INFO
135 #define CONFIG_SYS_FLASH_CFI
136 #define CONFIG_FLASH_CFI_DRIVER
138 #define CONFIG_FLASH_SHOW_PROGRESS 45
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1
141 #define CONFIG_SYS_MAX_FLASH_SECT 128
143 #define CONFIG_ENV_IS_IN_EEPROM
144 #ifdef CONFIG_ENV_IS_IN_EEPROM
145 #define CONFIG_ENV_OFFSET 0
146 #define CONFIG_ENV_SIZE 2048
149 #undef CONFIG_ENV_IS_IN_FLASH
150 #ifdef CONFIG_ENV_IS_IN_FLASH
151 #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
152 #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
156 #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
157 #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
158 #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
159 /*-----------------------------------------------------------------------
160 * SYPCR - System Protection Control
161 * SYPCR can only be written once after reset!
162 *-----------------------------------------------------------------------
165 #undef CONFIG_WATCHDOG
166 #if defined(CONFIG_WATCHDOG)
167 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
168 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
170 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
172 #endif /* CONFIG_WATCHDOG */
174 /*-----------------------------------------------------------------------
175 * TBSCR - Time Base Status and Control
176 *-----------------------------------------------------------------------
177 * Clear Reference Interrupt Status, Timebase freezing enabled
179 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
181 /*-----------------------------------------------------------------------
182 * PISCR - Periodic Interrupt Status and Control
183 *-----------------------------------------------------------------------
184 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
186 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
188 /*-----------------------------------------------------------------------
189 * SCCR - System Clock and reset Control Register
190 *-----------------------------------------------------------------------
191 * Set clock output, timebase and RTC source and divider,
192 * power management and some other internal clocks
194 #define SCCR_MASK SCCR_EBDF00
195 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
196 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
198 /*-----------------------------------------------------------------------
199 * SIUMCR - SIU Module Configuration
200 *-----------------------------------------------------------------------
203 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
205 /*-----------------------------------------------------------------------
206 * PLPRCR - PLL, Low-Power, and Reset Control Register
207 *-----------------------------------------------------------------------
208 * Set all bits to 40 Mhz
211 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
213 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
215 /*-----------------------------------------------------------------------
216 * UMCR - UIMB Module Configuration Register
217 *-----------------------------------------------------------------------
220 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
222 /*-----------------------------------------------------------------------
223 * ICTRL - I-Bus Support Control Register
225 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
227 /*-----------------------------------------------------------------------
228 * USIU - Memory Controller Register
229 *-----------------------------------------------------------------------
231 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
232 #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
234 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
235 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
237 #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
238 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
239 /* config registers: */
240 #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
241 #define CONFIG_SYS_OR3_PRELIM (0xffff0000)
243 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
245 /*-----------------------------------------------------------------------
246 * DER - Timer Decrementer
247 *-----------------------------------------------------------------------
250 #define CONFIG_SYS_DER 0x00000000
252 #endif /* __CONFIG_H */