3 * Denis Peter d.peter@mpl.ch
5 * SPDX-License-Identifier: GPL-2.0+
16 * High Level Configuration Options
19 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
20 #define CONFIG_PATI 1 /* ...On a PATI board */
22 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
24 /* Serial Console Configuration */
25 #define CONFIG_5xx_CONS_SCI1
26 #undef CONFIG_5xx_CONS_SCI2
31 #define CONFIG_BOOTP_BOOTFILESIZE
32 #define CONFIG_BOOTP_BOOTPATH
33 #define CONFIG_BOOTP_GATEWAY
34 #define CONFIG_BOOTP_HOSTNAME
37 * Command line configuration.
39 #define CONFIG_CMD_REGINFO
40 #define CONFIG_CMD_REGINFO
41 #define CONFIG_CMD_BSP
42 #define CONFIG_CMD_EEPROM
43 #define CONFIG_CMD_IRQ
45 #define CONFIG_BOOTCOMMAND "" /* autoboot command */
47 #define CONFIG_BOOTARGS "" /* */
49 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
51 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
54 * Miscellaneous configurable options
56 #define CONFIG_PREBOOT
58 #define CONFIG_SYS_LONGHELP /* undef to save memory */
59 #if defined(CONFIG_CMD_KGDB)
60 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
62 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
64 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
65 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
68 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
69 #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
71 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
73 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
75 /***********************************************************************
77 ***********************************************************************/
78 #define CONFIG_LAST_STAGE_INIT
81 * Low Level Configuration Settings
85 * Internal Memory Mapped (This is not the IMMR content)
87 #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
90 * Definitions for initial stack pointer and data area
92 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
93 #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
94 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
95 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
97 * Start addresses for the final memory configuration
98 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
100 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
101 #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
102 #define PCI_BASE 0x03000000 /* PCI Base (CS2) */
103 #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
104 #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
106 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
107 /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
108 /* This adress is given to the linker with -Ttext to */
109 /* locate the text section at this adress. */
110 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
111 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
113 #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
116 * For booting Linux, the board info and command line data
117 * have to be in the first 8 MB of memory, since this is
118 * the maximum mapped by the Linux kernel during initialization.
120 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
122 /*-----------------------------------------------------------------------
124 *-----------------------------------------------------------------------
128 #define CONFIG_SYS_FLASH_PROTECTION
129 #define CONFIG_SYS_FLASH_EMPTY_INFO
131 #define CONFIG_SYS_FLASH_CFI
132 #define CONFIG_FLASH_CFI_DRIVER
134 #define CONFIG_FLASH_SHOW_PROGRESS 45
136 #define CONFIG_SYS_MAX_FLASH_BANKS 1
137 #define CONFIG_SYS_MAX_FLASH_SECT 128
139 #define CONFIG_ENV_IS_IN_EEPROM
140 #ifdef CONFIG_ENV_IS_IN_EEPROM
141 #define CONFIG_ENV_OFFSET 0
142 #define CONFIG_ENV_SIZE 2048
145 #undef CONFIG_ENV_IS_IN_FLASH
146 #ifdef CONFIG_ENV_IS_IN_FLASH
147 #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
148 #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
152 #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
153 #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
154 #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
155 /*-----------------------------------------------------------------------
156 * SYPCR - System Protection Control
157 * SYPCR can only be written once after reset!
158 *-----------------------------------------------------------------------
161 #undef CONFIG_WATCHDOG
162 #if defined(CONFIG_WATCHDOG)
163 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
164 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
166 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
168 #endif /* CONFIG_WATCHDOG */
170 /*-----------------------------------------------------------------------
171 * TBSCR - Time Base Status and Control
172 *-----------------------------------------------------------------------
173 * Clear Reference Interrupt Status, Timebase freezing enabled
175 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
177 /*-----------------------------------------------------------------------
178 * PISCR - Periodic Interrupt Status and Control
179 *-----------------------------------------------------------------------
180 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
182 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
184 /*-----------------------------------------------------------------------
185 * SCCR - System Clock and reset Control Register
186 *-----------------------------------------------------------------------
187 * Set clock output, timebase and RTC source and divider,
188 * power management and some other internal clocks
190 #define SCCR_MASK SCCR_EBDF00
191 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
192 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
194 /*-----------------------------------------------------------------------
195 * SIUMCR - SIU Module Configuration
196 *-----------------------------------------------------------------------
199 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
201 /*-----------------------------------------------------------------------
202 * PLPRCR - PLL, Low-Power, and Reset Control Register
203 *-----------------------------------------------------------------------
204 * Set all bits to 40 Mhz
207 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
209 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
211 /*-----------------------------------------------------------------------
212 * UMCR - UIMB Module Configuration Register
213 *-----------------------------------------------------------------------
216 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
218 /*-----------------------------------------------------------------------
219 * ICTRL - I-Bus Support Control Register
221 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
223 /*-----------------------------------------------------------------------
224 * USIU - Memory Controller Register
225 *-----------------------------------------------------------------------
227 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
228 #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
230 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
231 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
233 #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
234 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
235 /* config registers: */
236 #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
237 #define CONFIG_SYS_OR3_PRELIM (0xffff0000)
239 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
241 /*-----------------------------------------------------------------------
242 * DER - Timer Decrementer
243 *-----------------------------------------------------------------------
246 #define CONFIG_SYS_DER 0x00000000
248 #endif /* __CONFIG_H */