include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
  19 #endif
  20
  21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  22 /* Set 1M boot space */
  23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  25                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  27 #endif
  28
  29 /* High Level Configuration Options */
  30 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  31
  32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  34 #endif
  35
  36 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  37 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  38 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  39 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  40 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  41 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  42
  43 #define CONFIG_SYS_SRIO
  44 #define CONFIG_SRIO1                    /* SRIO port 1 */
  45 #define CONFIG_SRIO2                    /* SRIO port 2 */
  46 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 #if defined(CONFIG_SPIFLASH)
  52 #elif defined(CONFIG_SDCARD)
  53         #define CONFIG_FSL_FIXED_MMC_LOCATION
  54         #define CONFIG_SYS_MMC_ENV_DEV          0
  55 #endif
  56
  57 #ifndef __ASSEMBLY__
  58 unsigned long get_board_sys_clk(unsigned long dummy);
  59 #endif
  60 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #define CONFIG_SYS_CACHE_STASHING
  66 #define CONFIG_BACKSIDE_L2_CACHE
  67 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  68 #define CONFIG_BTB                      /* toggle branch predition */
  69
  70 #define CONFIG_ENABLE_36BIT_PHYS
  71
  72 #ifdef CONFIG_PHYS_64BIT
  73 #define CONFIG_ADDR_MAP
  74 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  75 #endif
  76
  77 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  78 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  79 #define CONFIG_SYS_MEMTEST_END          0x00400000
  80
  81 /*
  82  *  Config the L3 Cache as L3 SRAM
  83  */
  84 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  85 #ifdef CONFIG_PHYS_64BIT
  86 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  87                 CONFIG_RAMBOOT_TEXT_BASE)
  88 #else
  89 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  90 #endif
  91 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  92 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  93
  94 #ifdef CONFIG_PHYS_64BIT
  95 #define CONFIG_SYS_DCSRBAR              0xf0000000
  96 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  97 #endif
  98
  99 /* EEPROM */
 100 #define CONFIG_ID_EEPROM
 101 #define CONFIG_SYS_I2C_EEPROM_NXID
 102 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 105
 106 /*
 107  * DDR Setup
 108  */
 109 #define CONFIG_VERY_BIG_RAM
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112
 113 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 114 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 115
 116 #define CONFIG_DDR_SPD
 117
 118 #define CONFIG_SYS_SPD_BUS_NUM  0
 119 #define SPD_EEPROM_ADDRESS      0x52
 120 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 121
 122 /*
 123  * Local Bus Definitions
 124  */
 125
 126 /* Set the local bus clock 1/8 of platform clock */
 127 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 128
 129 /*
 130  * This board doesn't have a promjet connector.
 131  * However, it uses commone corenet board LAW and TLB.
 132  * It is necessary to use the same start address with proper offset.
 133  */
 134 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 135 #ifdef CONFIG_PHYS_64BIT
 136 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 137 #else
 138 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 139 #endif
 140
 141 #define CONFIG_SYS_FLASH_BR_PRELIM \
 142                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 143                 BR_PS_16 | BR_V)
 144 #define CONFIG_SYS_FLASH_OR_PRELIM \
 145                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 146                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 147
 148 #define CONFIG_FSL_CPLD
 149 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 150 #ifdef CONFIG_PHYS_64BIT
 151 #define CPLD_BASE_PHYS          0xfffdf0000ull
 152 #else
 153 #define CPLD_BASE_PHYS          CPLD_BASE
 154 #endif
 155
 156 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 157 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 158
 159 #define PIXIS_LBMAP_SWITCH      7
 160 #define PIXIS_LBMAP_MASK        0xf0
 161 #define PIXIS_LBMAP_SHIFT       4
 162 #define PIXIS_LBMAP_ALTBANK     0x40
 163
 164 #define CONFIG_SYS_FLASH_QUIET_TEST
 165 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 166
 167 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 168 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 171
 172 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 173
 174 #if defined(CONFIG_RAMBOOT_PBL)
 175 #define CONFIG_SYS_RAMBOOT
 176 #endif
 177
 178 #define CONFIG_NAND_FSL_ELBC
 179 /* Nand Flash */
 180 #ifdef CONFIG_NAND_FSL_ELBC
 181 #define CONFIG_SYS_NAND_BASE            0xffa00000
 182 #ifdef CONFIG_PHYS_64BIT
 183 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 184 #else
 185 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 186 #endif
 187
 188 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 189 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 191
 192 /* NAND flash config */
 193 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 194                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 195                                | BR_PS_8               /* Port Size = 8 bit */ \
 196                                | BR_MS_FCM             /* MSEL = FCM */ \
 197                                | BR_V)                 /* valid */
 198 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 199                                | OR_FCM_PGS            /* Large Page*/ \
 200                                | OR_FCM_CSCT \
 201                                | OR_FCM_CST \
 202                                | OR_FCM_CHT \
 203                                | OR_FCM_SCY_1 \
 204                                | OR_FCM_TRLX \
 205                                | OR_FCM_EHTR)
 206
 207 #ifdef CONFIG_MTD_RAW_NAND
 208 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 209 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 210 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 211 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 212 #else
 213 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 214 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 215 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 216 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 217 #endif
 218 #else
 219 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 220 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 221 #endif /* CONFIG_NAND_FSL_ELBC */
 222
 223 #define CONFIG_SYS_FLASH_EMPTY_INFO
 224 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 225 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 226
 227 #define CONFIG_HWCONFIG
 228
 229 /* define to use L1 as initial stack */
 230 #define CONFIG_L1_INIT_RAM
 231 #define CONFIG_SYS_INIT_RAM_LOCK
 232 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 233 #ifdef CONFIG_PHYS_64BIT
 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 236 /* The assembler doesn't like typecast */
 237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 238         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 239           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 240 #else
 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 243 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 244 #endif
 245 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 246
 247 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 248                                         GENERATED_GBL_DATA_SIZE)
 249 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 250
 251 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 252 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 253
 254 /* Serial Port - controlled on board with jumper J8
 255  * open - index 2
 256  * shorted - index 1
 257  */
 258 #define CONFIG_SYS_NS16550_SERIAL
 259 #define CONFIG_SYS_NS16550_REG_SIZE     1
 260 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 261
 262 #define CONFIG_SYS_BAUDRATE_TABLE       \
 263         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 264
 265 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 266 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 267 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 268 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 269
 270 /* I2C */
 271 #ifndef CONFIG_DM_I2C
 272 #define CONFIG_SYS_I2C
 273 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 274 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 275 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 276 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 277 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 278 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 279 #else
 280 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 281 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 282 #endif
 283 #define CONFIG_SYS_I2C_FSL
 284
 285
 286 /*
 287  * RapidIO
 288  */
 289 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 290 #ifdef CONFIG_PHYS_64BIT
 291 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 292 #else
 293 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 294 #endif
 295 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 296
 297 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 298 #ifdef CONFIG_PHYS_64BIT
 299 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 300 #else
 301 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 302 #endif
 303 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 304
 305 /*
 306  * for slave u-boot IMAGE instored in master memory space,
 307  * PHYS must be aligned based on the SIZE
 308  */
 309 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 310 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 311 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 312 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 313 /*
 314  * for slave UCODE and ENV instored in master memory space,
 315  * PHYS must be aligned based on the SIZE
 316  */
 317 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 318 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 319 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 320
 321 /* slave core release by master*/
 322 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 323 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 324
 325 /*
 326  * SRIO_PCIE_BOOT - SLAVE
 327  */
 328 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 329 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 330 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 331                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 332 #endif
 333
 334 /*
 335  * eSPI - Enhanced SPI
 336  */
 337
 338 /*
 339  * General PCI
 340  * Memory space is mapped 1-1, but I/O space must start from 0.
 341  */
 342
 343 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 344 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 345 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 346 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 347 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 348
 349 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 350 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 351 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 352 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 353 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 354
 355 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 356 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 357 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 358 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 359 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 360
 361 /* Qman/Bman */
 362 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 363 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 364 #ifdef CONFIG_PHYS_64BIT
 365 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 366 #else
 367 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 368 #endif
 369 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 370 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 371 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 372 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 373 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 374 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 375                                         CONFIG_SYS_BMAN_CENA_SIZE)
 376 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 377 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 378 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 379 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 380 #ifdef CONFIG_PHYS_64BIT
 381 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 382 #else
 383 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 384 #endif
 385 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 386 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 387 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 388 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 389 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 390 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 391                                         CONFIG_SYS_QMAN_CENA_SIZE)
 392 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 393 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 394
 395 #define CONFIG_SYS_DPAA_FMAN
 396 #define CONFIG_SYS_DPAA_PME
 397 /* Default address of microcode for the Linux Fman driver */
 398 #if defined(CONFIG_SPIFLASH)
 399 /*
 400  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 401  * env, so we got 0x110000.
 402  */
 403 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 404 #elif defined(CONFIG_SDCARD)
 405 /*
 406  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 407  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 408  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 409  */
 410 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 411 #elif defined(CONFIG_MTD_RAW_NAND)
 412 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 413 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 414 /*
 415  * Slave has no ucode locally, it can fetch this from remote. When implementing
 416  * in two corenet boards, slave's ucode could be stored in master's memory
 417  * space, the address can be mapped from slave TLB->slave LAW->
 418  * slave SRIO or PCIE outbound window->master inbound window->
 419  * master LAW->the ucode address in master's memory space.
 420  */
 421 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 422 #else
 423 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 424 #endif
 425 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 426 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 427
 428 #ifdef CONFIG_PCI
 429 #if !defined(CONFIG_DM_PCI)
 430 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 431 #define CONFIG_PCI_INDIRECT_BRIDGE
 432 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 433 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 434 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 435 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 436 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 437 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 438 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 439 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 440 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 441 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 442 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 443 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 444 #endif
 445
 446 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 447 #endif  /* CONFIG_PCI */
 448
 449 /* SATA */
 450 #define CONFIG_FSL_SATA_V2
 451
 452 #ifdef CONFIG_FSL_SATA_V2
 453 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 454 #define CONFIG_SATA1
 455 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 456 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 457 #define CONFIG_SATA2
 458 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 459 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 460
 461 #define CONFIG_LBA48
 462 #endif
 463
 464 #ifdef CONFIG_FMAN_ENET
 465 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 466 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 467 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 468 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 469 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 470
 471 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 472 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 473 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 474 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 475
 476 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 477
 478 #define CONFIG_SYS_TBIPA_VALUE  8
 479 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 480 #endif
 481
 482 /*
 483  * Environment
 484  */
 485 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 486 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 487
 488 /*
 489  * Command line configuration.
 490  */
 491
 492 /*
 493 * USB
 494 */
 495 #define CONFIG_HAS_FSL_DR_USB
 496 #define CONFIG_HAS_FSL_MPH_USB
 497
 498 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 499 #define CONFIG_USB_EHCI_FSL
 500 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 501 #endif
 502
 503 #ifdef CONFIG_MMC
 504 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 505 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 506 #endif
 507
 508 /*
 509  * Miscellaneous configurable options
 510  */
 511 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 512
 513 /*
 514  * For booting Linux, the board info and command line data
 515  * have to be in the first 64 MB of memory, since this is
 516  * the maximum mapped by the Linux kernel during initialization.
 517  */
 518 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 519 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 520
 521 #ifdef CONFIG_CMD_KGDB
 522 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 523 #endif
 524
 525 /*
 526  * Environment Configuration
 527  */
 528 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 529 #define CONFIG_BOOTFILE         "uImage"
 530 #define CONFIG_UBOOTPATH        u-boot.bin
 531
 532 /* default location for tftp and bootm */
 533 #define CONFIG_LOADADDR         1000000
 534
 535 #define __USB_PHY_TYPE  utmi
 536
 537 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 538         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 539         "bank_intlv=cs0_cs1\0"                                  \
 540         "netdev=eth0\0"                                         \
 541         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 542         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 543         "tftpflash=tftpboot $loadaddr $uboot && "               \
 544         "protect off $ubootaddr +$filesize && "                 \
 545         "erase $ubootaddr +$filesize && "                       \
 546         "cp.b $loadaddr $ubootaddr $filesize && "               \
 547         "protect on $ubootaddr +$filesize && "                  \
 548         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 549         "consoledev=ttyS0\0"                                    \
 550         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 551         "usb_dr_mode=host\0"                                    \
 552         "ramdiskaddr=2000000\0"                                 \
 553         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 554         "fdtaddr=1e00000\0"                                     \
 555         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 556         "bdev=sda3\0"
 557
 558 #define CONFIG_HDBOOT                                   \
 559         "setenv bootargs root=/dev/$bdev rw "           \
 560         "console=$consoledev,$baudrate $othbootargs;"   \
 561         "tftp $loadaddr $bootfile;"                     \
 562         "tftp $fdtaddr $fdtfile;"                       \
 563         "bootm $loadaddr - $fdtaddr"
 564
 565 #define CONFIG_NFSBOOTCOMMAND                   \
 566         "setenv bootargs root=/dev/nfs rw "     \
 567         "nfsroot=$serverip:$rootpath "          \
 568         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 569         "console=$consoledev,$baudrate $othbootargs;"   \
 570         "tftp $loadaddr $bootfile;"             \
 571         "tftp $fdtaddr $fdtfile;"               \
 572         "bootm $loadaddr - $fdtaddr"
 573
 574 #define CONFIG_RAMBOOTCOMMAND                           \
 575         "setenv bootargs root=/dev/ram rw "             \
 576         "console=$consoledev,$baudrate $othbootargs;"   \
 577         "tftp $ramdiskaddr $ramdiskfile;"               \
 578         "tftp $loadaddr $bootfile;"                     \
 579         "tftp $fdtaddr $fdtfile;"                       \
 580         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 581
 582 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 583
 584 #include <asm/fsl_secure_boot.h>
 585
 586 #endif  /* __CONFIG_H */