2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #define CONFIG_P2041RDB
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
20 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24 /* Set 1M boot space */
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
27 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SYS_NO_FLASH
32 /* High Level Configuration Options */
34 #define CONFIG_E500 /* BOOKE e500 family */
35 #define CONFIG_E500MC /* BOOKE e500mc family */
36 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
37 #define CONFIG_MP /* support multiple processors */
39 #ifndef CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_TEXT_BASE 0xeff40000
43 #ifndef CONFIG_RESET_VECTOR_ADDRESS
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
48 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
49 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
50 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
51 #define CONFIG_PCIE1 /* PCIE controller 1 */
52 #define CONFIG_PCIE2 /* PCIE controller 2 */
53 #define CONFIG_PCIE3 /* PCIE controller 3 */
54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
57 #define CONFIG_SYS_SRIO
58 #define CONFIG_SRIO1 /* SRIO port 1 */
59 #define CONFIG_SRIO2 /* SRIO port 2 */
60 #define CONFIG_SRIO_PCIE_BOOT_MASTER
61 #define CONFIG_SYS_DPAA_RMAN /* RMan */
63 #define CONFIG_FSL_LAW /* Use common FSL init code */
65 #define CONFIG_ENV_OVERWRITE
67 #ifdef CONFIG_SYS_NO_FLASH
68 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
69 #define CONFIG_ENV_IS_NOWHERE
72 #define CONFIG_FLASH_CFI_DRIVER
73 #define CONFIG_SYS_FLASH_CFI
74 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
77 #if defined(CONFIG_SPIFLASH)
78 #define CONFIG_SYS_EXTRA_ENV_RELOC
79 #define CONFIG_ENV_IS_IN_SPI_FLASH
80 #define CONFIG_ENV_SPI_BUS 0
81 #define CONFIG_ENV_SPI_CS 0
82 #define CONFIG_ENV_SPI_MAX_HZ 10000000
83 #define CONFIG_ENV_SPI_MODE 0
84 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
85 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
86 #define CONFIG_ENV_SECT_SIZE 0x10000
87 #elif defined(CONFIG_SDCARD)
88 #define CONFIG_SYS_EXTRA_ENV_RELOC
89 #define CONFIG_ENV_IS_IN_MMC
90 #define CONFIG_FSL_FIXED_MMC_LOCATION
91 #define CONFIG_SYS_MMC_ENV_DEV 0
92 #define CONFIG_ENV_SIZE 0x2000
93 #define CONFIG_ENV_OFFSET (512 * 1658)
94 #elif defined(CONFIG_NAND)
95 #define CONFIG_SYS_EXTRA_ENV_RELOC
96 #define CONFIG_ENV_IS_IN_NAND
97 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
98 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
99 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
100 #define CONFIG_ENV_IS_IN_REMOTE
101 #define CONFIG_ENV_ADDR 0xffe20000
102 #define CONFIG_ENV_SIZE 0x2000
103 #elif defined(CONFIG_ENV_IS_NOWHERE)
104 #define CONFIG_ENV_SIZE 0x2000
106 #define CONFIG_ENV_IS_IN_FLASH
107 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
108 - CONFIG_ENV_SECT_SIZE)
109 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
114 unsigned long get_board_sys_clk(unsigned long dummy);
116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
119 * These can be toggled for performance analysis, otherwise use default.
121 #define CONFIG_SYS_CACHE_STASHING
122 #define CONFIG_BACKSIDE_L2_CACHE
123 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
124 #define CONFIG_BTB /* toggle branch predition */
126 #define CONFIG_ENABLE_36BIT_PHYS
128 #ifdef CONFIG_PHYS_64BIT
129 #define CONFIG_ADDR_MAP
130 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
133 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
134 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
135 #define CONFIG_SYS_MEMTEST_END 0x00400000
136 #define CONFIG_SYS_ALT_MEMTEST
137 #define CONFIG_PANIC_HANG /* do not reset board on panic */
140 * Config the L3 Cache as L3 SRAM
142 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
143 #ifdef CONFIG_PHYS_64BIT
144 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
145 CONFIG_RAMBOOT_TEXT_BASE)
147 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
149 #define CONFIG_SYS_L3_SIZE (1024 << 10)
150 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
152 #ifdef CONFIG_PHYS_64BIT
153 #define CONFIG_SYS_DCSRBAR 0xf0000000
154 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
158 #define CONFIG_ID_EEPROM
159 #define CONFIG_SYS_I2C_EEPROM_NXID
160 #define CONFIG_SYS_EEPROM_BUS_NUM 0
161 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167 #define CONFIG_VERY_BIG_RAM
168 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
169 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
171 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
172 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
174 #define CONFIG_DDR_SPD
175 #define CONFIG_SYS_FSL_DDR3
177 #define CONFIG_SYS_SPD_BUS_NUM 0
178 #define SPD_EEPROM_ADDRESS 0x52
179 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
182 * Local Bus Definitions
185 /* Set the local bus clock 1/8 of platform clock */
186 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
189 * This board doesn't have a promjet connector.
190 * However, it uses commone corenet board LAW and TLB.
191 * It is necessary to use the same start address with proper offset.
193 #define CONFIG_SYS_FLASH_BASE 0xe0000000
194 #ifdef CONFIG_PHYS_64BIT
195 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
197 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
200 #define CONFIG_SYS_FLASH_BR_PRELIM \
201 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
203 #define CONFIG_SYS_FLASH_OR_PRELIM \
204 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
205 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
207 #define CONFIG_FSL_CPLD
208 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
209 #ifdef CONFIG_PHYS_64BIT
210 #define CPLD_BASE_PHYS 0xfffdf0000ull
212 #define CPLD_BASE_PHYS CPLD_BASE
215 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
216 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
218 #define PIXIS_LBMAP_SWITCH 7
219 #define PIXIS_LBMAP_MASK 0xf0
220 #define PIXIS_LBMAP_SHIFT 4
221 #define PIXIS_LBMAP_ALTBANK 0x40
223 #define CONFIG_SYS_FLASH_QUIET_TEST
224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
226 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
233 #if defined(CONFIG_RAMBOOT_PBL)
234 #define CONFIG_SYS_RAMBOOT
237 #define CONFIG_NAND_FSL_ELBC
239 #ifdef CONFIG_NAND_FSL_ELBC
240 #define CONFIG_SYS_NAND_BASE 0xffa00000
241 #ifdef CONFIG_PHYS_64BIT
242 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
244 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
247 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
248 #define CONFIG_SYS_MAX_NAND_DEVICE 1
249 #define CONFIG_CMD_NAND
250 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
252 /* NAND flash config */
253 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
255 | BR_PS_8 /* Port Size = 8 bit */ \
256 | BR_MS_FCM /* MSEL = FCM */ \
258 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
259 | OR_FCM_PGS /* Large Page*/ \
268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
270 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
271 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
281 #endif /* CONFIG_NAND_FSL_ELBC */
283 #define CONFIG_SYS_FLASH_EMPTY_INFO
284 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
287 #define CONFIG_BOARD_EARLY_INIT_F
288 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
289 #define CONFIG_MISC_INIT_R
291 #define CONFIG_HWCONFIG
293 /* define to use L1 as initial stack */
294 #define CONFIG_L1_INIT_RAM
295 #define CONFIG_SYS_INIT_RAM_LOCK
296 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
297 #ifdef CONFIG_PHYS_64BIT
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
300 /* The assembler doesn't like typecast */
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
302 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
303 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
309 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
312 GENERATED_GBL_DATA_SIZE)
313 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
316 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
318 /* Serial Port - controlled on board with jumper J8
322 #define CONFIG_CONS_INDEX 1
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
327 #define CONFIG_SYS_BAUDRATE_TABLE \
328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
336 #define CONFIG_SYS_I2C
337 #define CONFIG_SYS_I2C_FSL
338 #define CONFIG_SYS_FSL_I2C_SPEED 400000
339 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
340 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
341 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
342 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
343 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
348 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
349 #ifdef CONFIG_PHYS_64BIT
350 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
352 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
354 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
356 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
357 #ifdef CONFIG_PHYS_64BIT
358 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
360 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
362 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
365 * for slave u-boot IMAGE instored in master memory space,
366 * PHYS must be aligned based on the SIZE
368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
373 * for slave UCODE and ENV instored in master memory space,
374 * PHYS must be aligned based on the SIZE
376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
380 /* slave core release by master*/
381 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
382 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
385 * SRIO_PCIE_BOOT - SLAVE
387 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
388 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
389 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
390 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
394 * eSPI - Enhanced SPI
396 #define CONFIG_SF_DEFAULT_SPEED 10000000
397 #define CONFIG_SF_DEFAULT_MODE 0
401 * Memory space is mapped 1-1, but I/O space must start from 0.
404 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
405 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
406 #ifdef CONFIG_PHYS_64BIT
407 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
408 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
410 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
411 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
413 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
414 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
415 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
419 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
421 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
423 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
424 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
427 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
429 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
430 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
432 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
433 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
434 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
438 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
440 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
442 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
443 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
446 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
451 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
452 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
453 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
459 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
462 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
463 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
464 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
465 #ifdef CONFIG_PHYS_64BIT
466 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
468 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
470 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
471 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
472 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
473 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
474 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
475 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
476 CONFIG_SYS_BMAN_CENA_SIZE)
477 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
478 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
479 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
480 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
481 #ifdef CONFIG_PHYS_64BIT
482 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
484 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
486 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
487 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
488 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
489 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
490 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
491 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
492 CONFIG_SYS_QMAN_CENA_SIZE)
493 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
494 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
496 #define CONFIG_SYS_DPAA_FMAN
497 #define CONFIG_SYS_DPAA_PME
498 /* Default address of microcode for the Linux Fman driver */
499 #if defined(CONFIG_SPIFLASH)
501 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
502 * env, so we got 0x110000.
504 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
505 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
506 #elif defined(CONFIG_SDCARD)
508 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
509 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
510 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
512 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
513 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
514 #elif defined(CONFIG_NAND)
515 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
516 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
517 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
519 * Slave has no ucode locally, it can fetch this from remote. When implementing
520 * in two corenet boards, slave's ucode could be stored in master's memory
521 * space, the address can be mapped from slave TLB->slave LAW->
522 * slave SRIO or PCIE outbound window->master inbound window->
523 * master LAW->the ucode address in master's memory space.
525 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
526 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
528 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
529 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
531 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
532 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
534 #ifdef CONFIG_SYS_DPAA_FMAN
535 #define CONFIG_FMAN_ENET
536 #define CONFIG_PHYLIB_10G
537 #define CONFIG_PHY_VITESSE
538 #define CONFIG_PHY_TERANETICS
542 #define CONFIG_PCI_INDIRECT_BRIDGE
544 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
545 #define CONFIG_DOS_PARTITION
546 #endif /* CONFIG_PCI */
549 #define CONFIG_FSL_SATA_V2
551 #ifdef CONFIG_FSL_SATA_V2
552 #define CONFIG_FSL_SATA
553 #define CONFIG_LIBATA
555 #define CONFIG_SYS_SATA_MAX_DEVICE 2
557 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
558 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
560 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
561 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
564 #define CONFIG_CMD_SATA
565 #define CONFIG_DOS_PARTITION
568 #ifdef CONFIG_FMAN_ENET
569 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
570 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
571 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
572 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
573 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
575 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
576 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
577 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
578 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
580 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
582 #define CONFIG_SYS_TBIPA_VALUE 8
583 #define CONFIG_MII /* MII PHY management */
584 #define CONFIG_ETHPRIME "FM1@DTSEC1"
585 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
591 #define CONFIG_LOADS_ECHO /* echo on for serial download */
592 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
595 * Command line configuration.
597 #define CONFIG_CMD_ERRATA
598 #define CONFIG_CMD_IRQ
601 #define CONFIG_CMD_PCI
607 #define CONFIG_HAS_FSL_DR_USB
608 #define CONFIG_HAS_FSL_MPH_USB
610 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
611 #define CONFIG_USB_EHCI
612 #define CONFIG_USB_EHCI_FSL
613 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
619 #define CONFIG_FSL_ESDHC
620 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
621 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
622 #define CONFIG_GENERIC_MMC
623 #define CONFIG_DOS_PARTITION
626 /* Hash command with SHA acceleration supported in hardware */
627 #ifdef CONFIG_FSL_CAAM
628 #define CONFIG_CMD_HASH
629 #define CONFIG_SHA_HW_ACCEL
633 * Miscellaneous configurable options
635 #define CONFIG_SYS_LONGHELP /* undef to save memory */
636 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
637 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
638 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
639 #ifdef CONFIG_CMD_KGDB
640 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
642 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
644 /* Print Buffer Size */
645 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
646 sizeof(CONFIG_SYS_PROMPT)+16)
647 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
648 /* Boot Argument Buffer Size */
649 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
652 * For booting Linux, the board info and command line data
653 * have to be in the first 64 MB of memory, since this is
654 * the maximum mapped by the Linux kernel during initialization.
656 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
657 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
659 #ifdef CONFIG_CMD_KGDB
660 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
664 * Environment Configuration
666 #define CONFIG_ROOTPATH "/opt/nfsroot"
667 #define CONFIG_BOOTFILE "uImage"
668 #define CONFIG_UBOOTPATH u-boot.bin
670 /* default location for tftp and bootm */
671 #define CONFIG_LOADADDR 1000000
674 #define CONFIG_BAUDRATE 115200
676 #define __USB_PHY_TYPE utmi
678 #define CONFIG_EXTRA_ENV_SETTINGS \
679 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
680 "bank_intlv=cs0_cs1\0" \
682 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
683 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
684 "tftpflash=tftpboot $loadaddr $uboot && " \
685 "protect off $ubootaddr +$filesize && " \
686 "erase $ubootaddr +$filesize && " \
687 "cp.b $loadaddr $ubootaddr $filesize && " \
688 "protect on $ubootaddr +$filesize && " \
689 "cmp.b $loadaddr $ubootaddr $filesize\0" \
690 "consoledev=ttyS0\0" \
691 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
692 "usb_dr_mode=host\0" \
693 "ramdiskaddr=2000000\0" \
694 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
695 "fdtaddr=1e00000\0" \
696 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
699 #define CONFIG_HDBOOT \
700 "setenv bootargs root=/dev/$bdev rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
706 #define CONFIG_NFSBOOTCOMMAND \
707 "setenv bootargs root=/dev/nfs rw " \
708 "nfsroot=$serverip:$rootpath " \
709 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
710 "console=$consoledev,$baudrate $othbootargs;" \
711 "tftp $loadaddr $bootfile;" \
712 "tftp $fdtaddr $fdtfile;" \
713 "bootm $loadaddr - $fdtaddr"
715 #define CONFIG_RAMBOOTCOMMAND \
716 "setenv bootargs root=/dev/ram rw " \
717 "console=$consoledev,$baudrate $othbootargs;" \
718 "tftp $ramdiskaddr $ramdiskfile;" \
719 "tftp $loadaddr $bootfile;" \
720 "tftp $fdtaddr $fdtfile;" \
721 "bootm $loadaddr $ramdiskaddr $fdtaddr"
723 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
725 #include <asm/fsl_secure_boot.h>
727 #endif /* __CONFIG_H */