sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / P2020DS.h
1 /*
2  * Copyright 2007-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * p2020ds board configuration file
9  *
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include "../board/freescale/common/ics307_clk.h"
15
16 #ifdef CONFIG_36BIT
17 #define CONFIG_PHYS_64BIT
18 #endif
19
20 #ifdef CONFIG_SDCARD
21 #define CONFIG_SYS_RAMBOOT
22 #define CONFIG_SYS_EXTRA_ENV_RELOC
23 #define CONFIG_SYS_TEXT_BASE            0xf8f40000
24 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
25 #endif
26
27 #ifdef CONFIG_SPIFLASH
28 #define CONFIG_SYS_RAMBOOT
29 #define CONFIG_SYS_EXTRA_ENV_RELOC
30 #define CONFIG_SYS_TEXT_BASE            0xf8f40000
31 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
32 #endif
33
34 /* High Level Configuration Options */
35 #define CONFIG_BOOKE            1       /* BOOKE */
36 #define CONFIG_E500             1       /* BOOKE e500 family */
37 #define CONFIG_P2020            1
38 #define CONFIG_P2020DS          1
39 #define CONFIG_MP               1       /* support multiple processors */
40
41 #ifndef CONFIG_SYS_TEXT_BASE
42 #define CONFIG_SYS_TEXT_BASE    0xeff40000
43 #endif
44
45 #ifndef CONFIG_RESET_VECTOR_ADDRESS
46 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
47 #endif
48
49 #define CONFIG_SYS_SRIO
50 #define CONFIG_SRIO1                    /* SRIO port 1 */
51 #define CONFIG_SRIO2                    /* SRIO port 2 */
52
53 #define CONFIG_FSL_ELBC         1       /* Has Enhanced localbus controller */
54 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
55 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
56 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
57 #define CONFIG_PCIE3            1       /* PCIE controler 3 (ULI bridge) */
58 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
59 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
60 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
61 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
62
63 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
64 #define CONFIG_E1000            1       /* Defind e1000 pci Ethernet card*/
65
66 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
67 #define CONFIG_ENV_OVERWRITE
68
69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
70 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk() /* ddrclk for MPC85xx */
71 #define CONFIG_ICS307_REFCLK_HZ 33333000  /* ICS307 clock chip ref freq */
72
73 /*
74  * These can be toggled for performance analysis, otherwise use default.
75  */
76 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
77 #define CONFIG_BTB                      /* toggle branch predition */
78
79 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
80
81 #define CONFIG_ENABLE_36BIT_PHYS        1
82
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_ADDR_MAP                 1
85 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
86 #endif
87
88 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
89 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END          0x00400000
91 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
92
93 /*
94  * Config the L2 Cache
95  */
96 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
99 #else
100 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
101 #endif
102 #define CONFIG_SYS_L2_SIZE              (512 << 10)
103 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
104
105 #define CONFIG_SYS_CCSRBAR              0xffe00000
106 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
107
108 /* DDR Setup */
109 #define CONFIG_VERY_BIG_RAM
110 #ifdef CONFIG_DDR2
111 #define CONFIG_SYS_FSL_DDR2
112 #else
113 #define CONFIG_SYS_FSL_DDR3             1
114 #endif
115
116 /* ECC will be enabled based on perf_mode environment variable */
117 /* #define      CONFIG_DDR_ECC */
118
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
121
122 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
123 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
124
125 #define CONFIG_NUM_DDR_CONTROLLERS      1
126 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
127 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
128
129 /* I2C addresses of SPD EEPROMs */
130 #define CONFIG_DDR_SPD
131 #define CONFIG_SYS_SPD_BUS_NUM          0       /* SPD EEPROM located on I2C bus 0 */
132 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
133
134 /* These are used when DDR doesn't use SPD.  */
135 #define CONFIG_SYS_SDRAM_SIZE           1024            /* DDR is 1GB */
136
137 /* Default settings for "stable" mode */
138 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
139 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
140 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
141 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
142 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
143 #define CONFIG_SYS_DDR_TIMING_0         0x00330804
144 #define CONFIG_SYS_DDR_TIMING_1         0x6f6b4846
145 #define CONFIG_SYS_DDR_TIMING_2         0x0fa890d4
146 #define CONFIG_SYS_DDR_MODE_1           0x00421422
147 #define CONFIG_SYS_DDR_MODE_2           0x00000000
148 #define CONFIG_SYS_DDR_MODE_CTRL        0x00000000
149 #define CONFIG_SYS_DDR_INTERVAL         0x61800100
150 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
151 #define CONFIG_SYS_DDR_CLK_CTRL         0x02000000
152 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
153 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
154 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
155 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8655A608
156 #define CONFIG_SYS_DDR_CONTROL          0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
157 #define CONFIG_SYS_DDR_CONTROL2         0x24400011
158 #define CONFIG_SYS_DDR_CDR1             0x00040000
159 #define CONFIG_SYS_DDR_CDR2             0x00000000
160
161 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
162 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
163 #define CONFIG_SYS_DDR_SBE              0x00010000
164
165 /* Settings that differ for "performance" mode */
166 #define CONFIG_SYS_DDR_CS0_BNDS_PERF            0x0000007F /* Interleaving Enabled */
167 #define CONFIG_SYS_DDR_CS1_BNDS_PERF            0x00000000 /* Interleaving Enabled */
168 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF  0x80014202
169 #define CONFIG_SYS_DDR_TIMING_1_PERF            0x5d5b4543
170 #define CONFIG_SYS_DDR_TIMING_2_PERF            0x0fa890ce
171 #define CONFIG_SYS_DDR_CONTROL_PERF             0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
172
173 /*
174  * The following set of values were tested for DDR2
175  * with a DDR3 to DDR2 interposer
176  *
177 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
178 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
179 #define CONFIG_SYS_DDR_TIMING_1         0x3935d322
180 #define CONFIG_SYS_DDR_TIMING_2         0x14904cc8
181 #define CONFIG_SYS_DDR_MODE_1           0x00480432
182 #define CONFIG_SYS_DDR_MODE_2           0x00000000
183 #define CONFIG_SYS_DDR_INTERVAL         0x06180100
184 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
185 #define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
186 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
187 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
188 #define CONFIG_SYS_DDR_CONTROL          0xC3008000
189 #define CONFIG_SYS_DDR_CONTROL2         0x04400010
190  *
191  */
192
193 /*
194  * Memory map
195  *
196  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
197  * 0x8000_0000  0xbfff_ffff     PCI Express Mem         1G non-cacheable
198  * 0xc000_0000  0xdfff_ffff     PCI                     512M non-cacheable
199  * 0xe100_0000  0xe3ff_ffff     PCI IO range            4M non-cacheable
200  *
201  * Localbus cacheable (TBD)
202  * 0xXXXX_XXXX  0xXXXX_XXXX     SRAM                    YZ M Cacheable
203  *
204  * Localbus non-cacheable
205  * 0xe000_0000  0xe80f_ffff     Promjet/free            128M non-cacheable
206  * 0xe800_0000  0xefff_ffff     FLASH                   128M non-cacheable
207  * 0xffa0_0000  0xffaf_ffff     NAND                    1M non-cacheable
208  * 0xffdf_0000  0xffdf_7fff     PIXIS                   32K non-cacheable TLB0
209  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
210  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
211  */
212
213 /*
214  * Local Bus Definitions
215  */
216 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* start of FLASH 128M */
217 #ifdef CONFIG_PHYS_64BIT
218 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
219 #else
220 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
221 #endif
222
223 #define CONFIG_FLASH_BR_PRELIM  \
224         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
225 #define CONFIG_FLASH_OR_PRELIM  0xf8000ff7
226
227 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
228 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
229
230 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
231 #define CONFIG_SYS_FLASH_QUIET_TEST
232 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233
234 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
235 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
236 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
237 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
238
239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
240
241 #define CONFIG_FLASH_CFI_DRIVER
242 #define CONFIG_SYS_FLASH_CFI
243 #define CONFIG_SYS_FLASH_EMPTY_INFO
244 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
245
246 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
247
248 #define CONFIG_HWCONFIG                 /* enable hwconfig */
249 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
250
251 #ifdef CONFIG_FSL_NGPIXIS
252 #define PIXIS_BASE      0xffdf0000      /* PIXIS registers */
253 #ifdef CONFIG_PHYS_64BIT
254 #define PIXIS_BASE_PHYS 0xfffdf0000ull
255 #else
256 #define PIXIS_BASE_PHYS PIXIS_BASE
257 #endif
258
259 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
260 #define CONFIG_SYS_OR3_PRELIM           0xffffeff7      /* 32KB but only 4k mapped */
261
262 #define PIXIS_LBMAP_SWITCH      7
263 #define PIXIS_LBMAP_MASK        0xf0
264 #define PIXIS_LBMAP_SHIFT       4
265 #define PIXIS_LBMAP_ALTBANK     0x20
266 #endif
267
268 #define CONFIG_SYS_INIT_RAM_LOCK        1
269 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
272 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
273 /* The assembler doesn't like typecast */
274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
275         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
276           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
277 #else
278 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
279 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
281 #endif
282 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000      /* Size of used area in RAM */
283
284 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
285 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
286
287 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
288 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
289
290 #define CONFIG_SYS_NAND_BASE            0xffa00000
291 #ifdef CONFIG_PHYS_64BIT
292 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
293 #else
294 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
295 #endif
296 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE,\
297                                 CONFIG_SYS_NAND_BASE + 0x40000, \
298                                 CONFIG_SYS_NAND_BASE + 0x80000,\
299                                 CONFIG_SYS_NAND_BASE + 0xC0000}
300 #define CONFIG_SYS_MAX_NAND_DEVICE      4
301 #define CONFIG_MTD_NAND_VERIFY_WRITE
302 #define CONFIG_CMD_NAND                 1
303 #define CONFIG_NAND_FSL_ELBC            1
304 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
305
306 /* NAND flash config */
307 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
308                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
309                                 | BR_PS_8               /* Port Size = 8bit */ \
310                                 | BR_MS_FCM             /* MSEL = FCM */ \
311                                 | BR_V)                 /* valid */
312 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000          /* length 256K */ \
313                                 | OR_FCM_PGS            /* Large Page*/ \
314                                 | OR_FCM_CSCT \
315                                 | OR_FCM_CST \
316                                 | OR_FCM_CHT \
317                                 | OR_FCM_SCY_1 \
318                                 | OR_FCM_TRLX \
319                                 | OR_FCM_EHTR)
320
321 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
322 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
323 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
324 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
325
326 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
327                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
328                                 | BR_PS_8               /* Port Size = 8bit */ \
329                                 | BR_MS_FCM             /* MSEL = FCM */ \
330                                 | BR_V)                 /* valid */
331 #define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
332 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
333                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
334                                 | BR_PS_8               /* Port Size = 8bit */ \
335                                 | BR_MS_FCM             /* MSEL = FCM */ \
336                                 | BR_V)                 /* valid */
337 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
338
339 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
340                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
341                                 | BR_PS_8               /* Port Size = 8bit */ \
342                                 | BR_MS_FCM             /* MSEL = FCM */ \
343                                 | BR_V)                 /* valid */
344 #define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM        /* NAND Options */
345
346 /* Serial Port - controlled on board with jumper J8
347  * open - index 2
348  * shorted - index 1
349  */
350 #define CONFIG_CONS_INDEX       1
351 #define CONFIG_SYS_NS16550
352 #define CONFIG_SYS_NS16550_SERIAL
353 #define CONFIG_SYS_NS16550_REG_SIZE     1
354 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
355
356 #define CONFIG_SYS_BAUDRATE_TABLE       \
357         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
358
359 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
360 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
361
362 /* Use the HUSH parser */
363 #define CONFIG_SYS_HUSH_PARSER
364
365 /*
366  * Pass open firmware flat tree
367  */
368 #define CONFIG_OF_LIBFDT                1
369 #define CONFIG_OF_BOARD_SETUP           1
370 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
371
372 /* I2C */
373 #define CONFIG_SYS_I2C
374 #define CONFIG_SYS_I2C_FSL
375 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
376 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
377 #define CONFIG_SYS_FSL_I2C_SPEED        400000
378 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
379 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
380 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
381 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
382 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
383
384 /*
385  * I2C2 EEPROM
386  */
387 #define CONFIG_ID_EEPROM
388 #ifdef CONFIG_ID_EEPROM
389 #define CONFIG_SYS_I2C_EEPROM_NXID
390 #endif
391 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
392 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
393 #define CONFIG_SYS_EEPROM_BUS_NUM       0
394
395 /*
396  * eSPI - Enhanced SPI
397  */
398 #define CONFIG_FSL_ESPI
399
400 #define CONFIG_SPI_FLASH
401 #define CONFIG_SPI_FLASH_SPANSION
402
403 #define CONFIG_CMD_SF
404 #define CONFIG_SF_DEFAULT_SPEED         10000000
405 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
406
407 /*
408  * General PCI
409  * Memory space is mapped 1-1, but I/O space must start from 0.
410  */
411
412 /* controller 3, Slot 1, tgtid 3, Base address b000 */
413 #define CONFIG_SYS_PCIE3_NAME           "Slot 1"
414 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
415 #ifdef CONFIG_PHYS_64BIT
416 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
417 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc00000000ull
418 #else
419 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
420 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
421 #endif
422 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
423 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
424 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE3_IO_PHYS        0xfffc00000ull
427 #else
428 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc00000
429 #endif
430 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
431
432 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
433 #define CONFIG_SYS_PCIE2_NAME           "ULI"
434 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
437 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
438 #else
439 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
440 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
441 #endif
442 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
443 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
444 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
445 #ifdef CONFIG_PHYS_64BIT
446 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
447 #else
448 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
449 #endif
450 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
451
452 /* controller 1, Slot 2, tgtid 1, Base address a000 */
453 #define CONFIG_SYS_PCIE1_NAME           "Slot 2"
454 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
455 #ifdef CONFIG_PHYS_64BIT
456 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
457 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
458 #else
459 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
460 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
461 #endif
462 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
463 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
464 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
465 #ifdef CONFIG_PHYS_64BIT
466 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
467 #else
468 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
469 #endif
470 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
471
472 #if defined(CONFIG_PCI)
473
474 /*PCIE video card used*/
475 #define VIDEO_IO_OFFSET         CONFIG_SYS_PCIE1_IO_VIRT
476
477 /* video */
478 #undef CONFIG_VIDEO
479
480 #if defined(CONFIG_VIDEO)
481 #define CONFIG_BIOSEMU
482 #define CONFIG_CFB_CONSOLE
483 #define CONFIG_VIDEO_SW_CURSOR
484 #define CONFIG_VGA_AS_SINGLE_DEVICE
485 #define CONFIG_ATI_RADEON_FB
486 #define CONFIG_VIDEO_LOGO
487 /*#define CONFIG_CONSOLE_CURSOR*/
488 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
489 #endif
490
491 /* SRIO1 uses the same window as PCIE2 mem window */
492 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
493 #ifdef CONFIG_PHYS_64BIT
494 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
495 #else
496 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
497 #endif
498 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
499
500 /* SRIO2 uses the same window as PCIE1 mem window */
501 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xc0000000
502 #ifdef CONFIG_PHYS_64BIT
503 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc40000000ull
504 #else
505 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc0000000
506 #endif
507 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x20000000      /* 512M */
508
509 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
510 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
511 #define CONFIG_DOS_PARTITION
512 #define CONFIG_SCSI_AHCI
513
514 #ifdef CONFIG_SCSI_AHCI
515 #define CONFIG_LIBATA
516 #define CONFIG_SATA_ULI5288
517 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
518 #define CONFIG_SYS_SCSI_MAX_LUN 1
519 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
520 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
521 #endif /* SCSI */
522
523 #endif  /* CONFIG_PCI */
524
525
526 #if defined(CONFIG_TSEC_ENET)
527
528 #define CONFIG_MII              1       /* MII PHY management */
529 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
530 #define CONFIG_TSEC1    1
531 #define CONFIG_TSEC1_NAME       "eTSEC1"
532 #define CONFIG_TSEC2    1
533 #define CONFIG_TSEC2_NAME       "eTSEC2"
534 #define CONFIG_TSEC3    1
535 #define CONFIG_TSEC3_NAME       "eTSEC3"
536
537 #define CONFIG_FSL_SGMII_RISER  1
538 #define SGMII_RISER_PHY_OFFSET  0x1b
539
540 #ifdef CONFIG_FSL_SGMII_RISER
541 #define CONFIG_SYS_TBIPA_VALUE          0x10 /* avoid conflict with eTSEC4 paddr */
542 #endif
543
544 #define TSEC1_PHY_ADDR          0
545 #define TSEC2_PHY_ADDR          1
546 #define TSEC3_PHY_ADDR          2
547
548 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
549 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
550 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
551
552 #define TSEC1_PHYIDX            0
553 #define TSEC2_PHYIDX            0
554 #define TSEC3_PHYIDX            0
555
556 #define CONFIG_ETHPRIME         "eTSEC1"
557
558 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
559 #endif  /* CONFIG_TSEC_ENET */
560
561 /*
562  * Environment
563  */
564 #if defined(CONFIG_SDCARD)
565 #define CONFIG_ENV_IS_IN_MMC
566 #define CONFIG_FSL_FIXED_MMC_LOCATION
567 #define CONFIG_ENV_SIZE                 0x2000
568 #define CONFIG_SYS_MMC_ENV_DEV          0
569 #elif defined(CONFIG_SPIFLASH)
570 #define CONFIG_ENV_IS_IN_SPI_FLASH
571 #define CONFIG_ENV_SPI_BUS              0
572 #define CONFIG_ENV_SPI_CS               0
573 #define CONFIG_ENV_SPI_MAX_HZ           10000000
574 #define CONFIG_ENV_SPI_MODE             0
575 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
576 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
577 #define CONFIG_ENV_SECT_SIZE            0x10000
578 #else
579 #define CONFIG_ENV_IS_IN_FLASH  1
580 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
581 #define CONFIG_ENV_SIZE         0x2000
582 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
583 #endif
584
585 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
586 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
587
588 /*
589  * Command line configuration.
590  */
591 #include <config_cmd_default.h>
592
593 #define CONFIG_CMD_IRQ
594 #define CONFIG_CMD_PING
595 #define CONFIG_CMD_I2C
596 #define CONFIG_CMD_MII
597 #define CONFIG_CMD_ELF
598 #define CONFIG_CMD_IRQ
599 #define CONFIG_CMD_SETEXPR
600 #define CONFIG_CMD_REGINFO
601
602 #if defined(CONFIG_PCI)
603 #define CONFIG_CMD_PCI
604 #define CONFIG_CMD_NET
605 #define CONFIG_CMD_SCSI
606 #define CONFIG_CMD_EXT2
607 #endif
608
609 /*
610  * USB
611  */
612 #define CONFIG_HAS_FSL_DR_USB
613 #ifdef CONFIG_HAS_FSL_DR_USB
614 #define CONFIG_USB_EHCI
615
616 #ifdef CONFIG_USB_EHCI
617 #define CONFIG_CMD_USB
618 #define CONFIG_USB_STORAGE
619 #define CONFIG_USB_EHCI_FSL
620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
621 #endif
622 #endif
623
624 /*
625  * SDHC/MMC
626  */
627 #define CONFIG_MMC
628
629 #ifdef CONFIG_MMC
630 #define CONFIG_FSL_ESDHC
631 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
632 #define CONFIG_CMD_MMC
633 #define CONFIG_GENERIC_MMC
634 #endif
635
636 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
637 #define CONFIG_CMD_EXT2
638 #define CONFIG_CMD_FAT
639 #define CONFIG_DOS_PARTITION
640 #endif
641
642 /*
643  * Miscellaneous configurable options
644  */
645 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
646 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
647 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
648 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
649 #if defined(CONFIG_CMD_KGDB)
650 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
651 #else
652 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
653 #endif
654 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
655 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
656 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
657
658 /*
659  * For booting Linux, the board info and command line data
660  * have to be in the first 64 MB of memory, since this is
661  * the maximum mapped by the Linux kernel during initialization.
662  */
663 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
664 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
665
666 #if defined(CONFIG_CMD_KGDB)
667 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
668 #endif
669
670 /*
671  * Environment Configuration
672  */
673
674 /* The mac addresses for all ethernet interface */
675 #if defined(CONFIG_TSEC_ENET)
676 #define CONFIG_HAS_ETH0
677 #define CONFIG_HAS_ETH1
678 #define CONFIG_HAS_ETH2
679 #endif
680
681 #define CONFIG_IPADDR           192.168.1.254
682
683 #define CONFIG_HOSTNAME         unknown
684 #define CONFIG_ROOTPATH         "/opt/nfsroot"
685 #define CONFIG_BOOTFILE         "uImage"
686 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
687
688 #define CONFIG_SERVERIP         192.168.1.1
689 #define CONFIG_GATEWAYIP        192.168.1.1
690 #define CONFIG_NETMASK          255.255.255.0
691
692 /* default location for tftp and bootm */
693 #define CONFIG_LOADADDR         1000000
694
695 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
696
697 #define CONFIG_BAUDRATE 115200
698
699 #define CONFIG_EXTRA_ENV_SETTINGS                               \
700 "perf_mode=performance\0"                       \
701         "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"  \
702         "usb1:dr_mode=host,phy_type=ulpi\0"                     \
703 "netdev=eth0\0"                                         \
704 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
705 "tftpflash=tftpboot $loadaddr $uboot; "                 \
706         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
707         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
708         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
709         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
710         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
711 "satabootcmd=setenv bootargs root=/dev/$bdev rw "       \
712         "console=$consoledev,$baudrate $othbootargs;"   \
713         "tftp $loadaddr $bootfile;"                     \
714         "tftp $fdtaddr $fdtfile;"                       \
715         "bootm $loadaddr - $fdtaddr"                    \
716 "consoledev=ttyS0\0"                            \
717 "ramdiskaddr=2000000\0"                 \
718 "ramdiskfile=p2020ds/ramdisk.uboot\0"           \
719 "fdtaddr=c00000\0"                              \
720 "othbootargs=cache-sram-size=0x10000\0" \
721 "fdtfile=p2020ds/p2020ds.dtb\0"         \
722 "bdev=sda3\0"                                   \
723 "partition=scsi 0:0\0"
724
725 #define CONFIG_HDBOOT                           \
726  "setenv bootargs root=/dev/$bdev rw "          \
727  "console=$consoledev,$baudrate $othbootargs;"  \
728  "ext2load $partition $loadaddr $bootfile;"     \
729  "ext2load $partition $fdtaddr $fdtfile;"       \
730  "bootm $loadaddr - $fdtaddr"
731
732 #define CONFIG_NFSBOOTCOMMAND           \
733  "setenv bootargs root=/dev/nfs rw "    \
734  "nfsroot=$serverip:$rootpath "         \
735  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
736  "console=$consoledev,$baudrate $othbootargs;"  \
737  "tftp $loadaddr $bootfile;"            \
738  "tftp $fdtaddr $fdtfile;"              \
739  "bootm $loadaddr - $fdtaddr"
740
741 #define CONFIG_RAMBOOTCOMMAND           \
742  "setenv bootargs root=/dev/ram rw "    \
743  "console=$consoledev,$baudrate $othbootargs;"  \
744  "tftp $ramdiskaddr $ramdiskfile;"      \
745  "tftp $loadaddr $bootfile;"            \
746  "tftp $fdtaddr $fdtfile;"              \
747  "bootm $loadaddr $ramdiskaddr $fdtaddr"
748
749 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
750
751 #endif  /* __CONFIG_H */