2 * Copyright 2007-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * p2020ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_P2020 1
35 #define CONFIG_P2020DS 1
36 #define CONFIG_MP 1 /* support multiple processors */
38 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
39 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
48 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
50 #define CONFIG_TSEC_ENET /* tsec ethernet support */
51 #define CONFIG_ENV_OVERWRITE
54 * When initializing flash, if we cannot find the manufacturer ID,
55 * assume this is the AMD flash associated with the CDS board.
56 * This allows booting from a promjet.
58 #define CONFIG_ASSUME_AMD_FLASH
61 extern unsigned long calculate_board_sys_clk(unsigned long dummy);
62 extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
63 /* extern unsigned long get_board_sys_clk(unsigned long dummy); */
64 /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
66 #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
67 #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
68 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
69 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
70 from ICS307 instead of switches */
73 * These can be toggled for performance analysis, otherwise use default.
75 #define CONFIG_L2_CACHE /* toggle L2 cache */
76 #define CONFIG_BTB /* toggle branch predition */
78 #define CONFIG_ENABLE_36BIT_PHYS 1
80 #ifdef CONFIG_PHYS_64BIT
81 #define CONFIG_ADDR_MAP 1
82 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
85 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
86 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
87 #define CONFIG_PANIC_HANG /* do not reset board on panic */
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
93 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
98 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
100 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
102 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
103 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
104 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
107 #define CONFIG_SYS_DDR_TLB_START 9
108 #define CONFIG_VERY_BIG_RAM
109 #define CONFIG_FSL_DDR3 1
110 #undef CONFIG_FSL_DDR_INTERACTIVE
112 /* ECC will be enabled based on perf_mode environment variable */
113 /* #define CONFIG_DDR_ECC */
115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
116 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_NUM_DDR_CONTROLLERS 1
122 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
123 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
125 /* I2C addresses of SPD EEPROMs */
126 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
127 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
129 /* These are used when DDR doesn't use SPD. */
130 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
132 /* Default settings for "stable" mode */
133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
134 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
136 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
137 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
138 #define CONFIG_SYS_DDR_TIMING_0 0x00330804
139 #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
140 #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
141 #define CONFIG_SYS_DDR_MODE_1 0x00421422
142 #define CONFIG_SYS_DDR_MODE_2 0x00000000
143 #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
144 #define CONFIG_SYS_DDR_INTERVAL 0x61800100
145 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
146 #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
147 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
148 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
149 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
150 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
151 #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
152 #define CONFIG_SYS_DDR_CONTROL2 0x24400011
153 #define CONFIG_SYS_DDR_CDR1 0x00040000
154 #define CONFIG_SYS_DDR_CDR2 0x00000000
156 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
157 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
158 #define CONFIG_SYS_DDR_SBE 0x00010000
160 /* Settings that differ for "performance" mode */
161 #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
162 #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
163 #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
164 #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
165 #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
166 #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
169 * The following set of values were tested for DDR2
170 * with a DDR3 to DDR2 interposer
172 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
173 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
174 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
175 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
176 #define CONFIG_SYS_DDR_MODE_1 0x00480432
177 #define CONFIG_SYS_DDR_MODE_2 0x00000000
178 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
179 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
180 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
181 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
182 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
183 #define CONFIG_SYS_DDR_CONTROL 0xC3008000
184 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
188 #undef CONFIG_CLOCKS_IN_MHZ
193 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
194 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
195 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
196 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
198 * Localbus cacheable (TBD)
199 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
201 * Localbus non-cacheable
202 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
203 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
204 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
205 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
206 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
207 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
211 * Local Bus Definitions
213 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
214 #ifdef CONFIG_PHYS_64BIT
215 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
217 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
220 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
221 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
223 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
224 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
226 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
227 #define CONFIG_SYS_FLASH_QUIET_TEST
228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
232 #undef CONFIG_SYS_FLASH_CHECKSUM
233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
236 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
238 #define CONFIG_FLASH_CFI_DRIVER
239 #define CONFIG_SYS_FLASH_CFI
240 #define CONFIG_SYS_FLASH_EMPTY_INFO
241 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
243 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
245 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
246 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
247 #ifdef CONFIG_PHYS_64BIT
248 #define PIXIS_BASE_PHYS 0xfffdf0000ull
250 #define PIXIS_BASE_PHYS PIXIS_BASE
253 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
254 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
256 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
257 #define PIXIS_VER 0x1 /* Board version at offset 1 */
258 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
259 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
260 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
261 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
262 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
263 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
264 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
265 #define PIXIS_VCTL 0x10 /* VELA Control Register */
266 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
267 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
268 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
269 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
270 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
271 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
272 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
273 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
274 #define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
275 #define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
276 #define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
277 #define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
278 #define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
279 #define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
281 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
282 #define PIXIS_LED 0x25 /* LED Register */
284 #define PIXIS_SW(x) 0x20 + (x - 1) * 2
285 #define PIXIS_EN(x) 0x21 + (x - 1) * 2
286 #define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
287 #define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
289 /* old pixis referenced names */
290 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
291 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
292 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
293 #define PIXIS_VSPEED2_TSEC1SER 0x8
294 #define PIXIS_VSPEED2_TSEC2SER 0x4
295 #define PIXIS_VSPEED2_TSEC3SER 0x2
296 #define PIXIS_VSPEED2_TSEC4SER 0x1
297 #define PIXIS_VCFGEN1_TSEC1SER 0x20
298 #define PIXIS_VCFGEN1_TSEC2SER 0x20
299 #define PIXIS_VCFGEN1_TSEC3SER 0x20
300 #define PIXIS_VCFGEN1_TSEC4SER 0x20
301 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
302 | PIXIS_VSPEED2_TSEC2SER \
303 | PIXIS_VSPEED2_TSEC3SER \
304 | PIXIS_VSPEED2_TSEC4SER)
305 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
306 | PIXIS_VCFGEN1_TSEC2SER \
307 | PIXIS_VCFGEN1_TSEC3SER \
308 | PIXIS_VCFGEN1_TSEC4SER)
310 #define CONFIG_SYS_INIT_RAM_LOCK 1
311 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
312 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
314 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
315 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
318 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
319 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
321 #define CONFIG_SYS_NAND_BASE 0xffa00000
322 #ifdef CONFIG_PHYS_64BIT
323 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
325 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
327 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
328 CONFIG_SYS_NAND_BASE + 0x40000, \
329 CONFIG_SYS_NAND_BASE + 0x80000,\
330 CONFIG_SYS_NAND_BASE + 0xC0000}
331 #define CONFIG_SYS_MAX_NAND_DEVICE 4
332 #define CONFIG_MTD_NAND_VERIFY_WRITE
333 #define CONFIG_CMD_NAND 1
334 #define CONFIG_NAND_FSL_ELBC 1
335 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
337 /* NAND flash config */
338 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
339 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
340 | BR_PS_8 /* Port Size = 8bit */ \
341 | BR_MS_FCM /* MSEL = FCM */ \
343 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
344 | OR_FCM_PGS /* Large Page*/ \
352 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
353 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
354 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
355 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
357 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
358 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
359 | BR_PS_8 /* Port Size = 8bit */ \
360 | BR_MS_FCM /* MSEL = FCM */ \
362 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
363 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
364 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
365 | BR_PS_8 /* Port Size = 8bit */ \
366 | BR_MS_FCM /* MSEL = FCM */ \
368 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
370 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
371 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
372 | BR_PS_8 /* Port Size = 8bit */ \
373 | BR_MS_FCM /* MSEL = FCM */ \
375 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
377 /* Serial Port - controlled on board with jumper J8
381 #define CONFIG_CONS_INDEX 1
382 #undef CONFIG_SERIAL_SOFTWARE_FIFO
383 #define CONFIG_SYS_NS16550
384 #define CONFIG_SYS_NS16550_SERIAL
385 #define CONFIG_SYS_NS16550_REG_SIZE 1
386 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
388 #define CONFIG_SYS_BAUDRATE_TABLE \
389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
391 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
392 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
394 /* Use the HUSH parser */
395 #define CONFIG_SYS_HUSH_PARSER
396 #ifdef CONFIG_SYS_HUSH_PARSER
397 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
401 * Pass open firmware flat tree
403 #define CONFIG_OF_LIBFDT 1
404 #define CONFIG_OF_BOARD_SETUP 1
405 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
407 #define CONFIG_SYS_64BIT_VSPRINTF 1
408 #define CONFIG_SYS_64BIT_STRTOUL 1
410 /* new uImage format support */
412 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
415 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
416 #define CONFIG_HARD_I2C /* I2C with hardware support */
417 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
418 #define CONFIG_I2C_MULTI_BUS
419 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
420 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
421 #define CONFIG_SYS_I2C_SLAVE 0x7F
422 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
423 #define CONFIG_SYS_I2C_OFFSET 0x3000
424 #define CONFIG_SYS_I2C2_OFFSET 0x3100
429 #define CONFIG_ID_EEPROM
430 #ifdef CONFIG_ID_EEPROM
431 #define CONFIG_SYS_I2C_EEPROM_NXID
433 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
434 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
435 #define CONFIG_SYS_EEPROM_BUS_NUM 0
439 * Memory space is mapped 1-1, but I/O space must start from 0.
442 /* controller 3, Slot 1, tgtid 3, Base address b000 */
443 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
444 #ifdef CONFIG_PHYS_64BIT
445 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
446 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
448 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
451 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
452 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
453 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
459 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
461 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
462 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
463 #ifdef CONFIG_PHYS_64BIT
464 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
465 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
467 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
468 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
470 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
471 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
472 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
476 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
478 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
480 /* controller 1, Slot 2, tgtid 1, Base address a000 */
481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
482 #ifdef CONFIG_PHYS_64BIT
483 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
486 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
487 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
489 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
490 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
491 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
492 #ifdef CONFIG_PHYS_64BIT
493 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
497 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
499 #if defined(CONFIG_PCI)
501 /*PCIE video card used*/
502 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
507 #if defined(CONFIG_VIDEO)
508 #define CONFIG_BIOSEMU
509 #define CONFIG_CFB_CONSOLE
510 #define CONFIG_VIDEO_SW_CURSOR
511 #define CONFIG_VGA_AS_SINGLE_DEVICE
512 #define CONFIG_ATI_RADEON_FB
513 #define CONFIG_VIDEO_LOGO
514 /*#define CONFIG_CONSOLE_CURSOR*/
515 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
518 #define CONFIG_NET_MULTI
519 #define CONFIG_PCI_PNP /* do pci plug-and-play */
521 #undef CONFIG_EEPRO100
523 #define CONFIG_RTL8139
525 #ifndef CONFIG_PCI_PNP
526 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
527 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
528 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
531 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
532 #define CONFIG_DOS_PARTITION
533 #define CONFIG_SCSI_AHCI
535 #ifdef CONFIG_SCSI_AHCI
536 #define CONFIG_SATA_ULI5288
537 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
538 #define CONFIG_SYS_SCSI_MAX_LUN 1
539 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
540 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
543 #endif /* CONFIG_PCI */
546 #if defined(CONFIG_TSEC_ENET)
548 #ifndef CONFIG_NET_MULTI
549 #define CONFIG_NET_MULTI 1
552 #define CONFIG_MII 1 /* MII PHY management */
553 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
554 #define CONFIG_TSEC1 1
555 #define CONFIG_TSEC1_NAME "eTSEC1"
556 #define CONFIG_TSEC2 1
557 #define CONFIG_TSEC2_NAME "eTSEC2"
558 #define CONFIG_TSEC3 1
559 #define CONFIG_TSEC3_NAME "eTSEC3"
561 #define CONFIG_PIXIS_SGMII_CMD
562 #define CONFIG_FSL_SGMII_RISER 1
563 #define SGMII_RISER_PHY_OFFSET 0x1b
565 #ifdef CONFIG_FSL_SGMII_RISER
566 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
569 #define TSEC1_PHY_ADDR 0
570 #define TSEC2_PHY_ADDR 1
571 #define TSEC3_PHY_ADDR 2
573 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
574 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
575 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
577 #define TSEC1_PHYIDX 0
578 #define TSEC2_PHYIDX 0
579 #define TSEC3_PHYIDX 0
581 #define CONFIG_ETHPRIME "eTSEC1"
583 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
584 #endif /* CONFIG_TSEC_ENET */
589 #define CONFIG_ENV_IS_IN_FLASH 1
590 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
591 #define CONFIG_ENV_ADDR 0xfff80000
593 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
595 #define CONFIG_ENV_SIZE 0x2000
596 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
598 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
599 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
602 * Command line configuration.
604 #include <config_cmd_default.h>
606 #define CONFIG_CMD_IRQ
607 #define CONFIG_CMD_PING
608 #define CONFIG_CMD_I2C
609 #define CONFIG_CMD_MII
610 #define CONFIG_CMD_ELF
611 #define CONFIG_CMD_IRQ
612 #define CONFIG_CMD_SETEXPR
614 #if defined(CONFIG_PCI)
615 #define CONFIG_CMD_PCI
616 #define CONFIG_CMD_NET
617 #define CONFIG_CMD_SCSI
618 #define CONFIG_CMD_EXT2
624 #define CONFIG_CMD_USB
625 #define CONFIG_USB_STORAGE
626 #define CONFIG_USB_EHCI
627 #define CONFIG_USB_EHCI_FSL
628 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
630 #undef CONFIG_WATCHDOG /* watchdog disabled */
633 * Miscellaneous configurable options
635 #define CONFIG_SYS_LONGHELP /* undef to save memory */
636 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
637 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
638 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
639 #if defined(CONFIG_CMD_KGDB)
640 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
642 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
644 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
645 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
646 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
647 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
650 * For booting Linux, the board info and command line data
651 * have to be in the first 16 MB of memory, since this is
652 * the maximum mapped by the Linux kernel during initialization.
654 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
657 * Internal Definitions
661 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
662 #define BOOTFLAG_WARM 0x02 /* Software reboot */
664 #if defined(CONFIG_CMD_KGDB)
665 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
666 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
670 * Environment Configuration
673 /* The mac addresses for all ethernet interface */
674 #if defined(CONFIG_TSEC_ENET)
675 #define CONFIG_HAS_ETH0
676 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
677 #define CONFIG_HAS_ETH1
678 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
679 #define CONFIG_HAS_ETH2
680 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
681 #define CONFIG_HAS_ETH3
682 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
685 #define CONFIG_IPADDR 192.168.1.254
687 #define CONFIG_HOSTNAME unknown
688 #define CONFIG_ROOTPATH /opt/nfsroot
689 #define CONFIG_BOOTFILE uImage
690 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
692 #define CONFIG_SERVERIP 192.168.1.1
693 #define CONFIG_GATEWAYIP 192.168.1.1
694 #define CONFIG_NETMASK 255.255.255.0
696 /* default location for tftp and bootm */
697 #define CONFIG_LOADADDR 1000000
699 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
700 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
702 #define CONFIG_BAUDRATE 115200
704 #define CONFIG_EXTRA_ENV_SETTINGS \
705 "perf_mode=stable\0" \
706 "memctl_intlv_ctl=2\0" \
708 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
709 "tftpflash=tftpboot $loadaddr $uboot; " \
710 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
711 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
712 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
713 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
714 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
715 "consoledev=ttyS0\0" \
716 "ramdiskaddr=2000000\0" \
717 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
719 "fdtfile=p2020ds/p2020ds.dtb\0" \
722 #define CONFIG_HDBOOT \
723 "setenv bootargs root=/dev/$bdev rw " \
724 "console=$consoledev,$baudrate $othbootargs;" \
725 "tftp $loadaddr $bootfile;" \
726 "tftp $fdtaddr $fdtfile;" \
727 "bootm $loadaddr - $fdtaddr"
729 #define CONFIG_NFSBOOTCOMMAND \
730 "setenv bootargs root=/dev/nfs rw " \
731 "nfsroot=$serverip:$rootpath " \
732 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
733 "console=$consoledev,$baudrate $othbootargs;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr - $fdtaddr"
738 #define CONFIG_RAMBOOTCOMMAND \
739 "setenv bootargs root=/dev/ram rw " \
740 "console=$consoledev,$baudrate $othbootargs;" \
741 "tftp $ramdiskaddr $ramdiskfile;" \
742 "tftp $loadaddr $bootfile;" \
743 "tftp $fdtaddr $fdtfile;" \
744 "bootm $loadaddr $ramdiskaddr $fdtaddr"
746 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
748 #endif /* __CONFIG_H */