sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / P2020COME.h
1 /*
2  * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /* The P2020COME board is only booted via the Freescale On-Chip ROM */
11 #define CONFIG_SYS_RAMBOOT
12 #define CONFIG_SYS_EXTRA_ENV_RELOC
13
14 #define CONFIG_SYS_TEXT_BASE            0xf8f80000
15 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
16
17 #ifdef CONFIG_SDCARD
18 #define CONFIG_RAMBOOT_SDCARD           1
19 #endif
20
21 #ifdef CONFIG_SPIFLASH
22 #define CONFIG_RAMBOOT_SPIFLASH         1
23 #endif
24
25 #ifndef CONFIG_SYS_MONITOR_BASE
26 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
27 #endif
28
29 /* High Level Configuration Options */
30 #define CONFIG_BOOKE            1       /* BOOKE */
31 #define CONFIG_E500             1       /* BOOKE e500 family */
32 #define CONFIG_P2020            1
33 #define CONFIG_P2020COME        1
34 #define CONFIG_FSL_ELBC         1       /* Enable eLBC Support */
35 #define CONFIG_MP
36
37 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
38 #if defined(CONFIG_PCI)
39 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
40 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
41 #define CONFIG_PCIE3            1       /* PCIE controller 3 (slot 3) */
42
43 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
44 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
45 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
46 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
47 #endif /* #if defined(CONFIG_PCI) */
48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
49 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
50 #define CONFIG_ENV_OVERWRITE
51
52 #if defined(CONFIG_PCI)
53 #define CONFIG_E1000            1       /* E1000 pci Ethernet card */
54 #endif
55
56 #ifndef __ASSEMBLY__
57 extern unsigned long get_board_ddr_clk(unsigned long dummy);
58 extern unsigned long get_board_sys_clk(unsigned long dummy);
59 #endif
60
61 /*
62  * For P2020COME DDRCLK and SYSCLK are from the same oscillator
63  * For DA phase the SYSCLK is 66MHz
64  * For EA phase the SYSCLK is 100MHz
65  */
66 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0)
67 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
68
69 #define CONFIG_HWCONFIG
70
71 /*
72  * These can be toggled for performance analysis, otherwise use default.
73  */
74 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
75 #define CONFIG_BTB                      /* toggle branch prediction */
76
77 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
78
79 #define CONFIG_ENABLE_36BIT_PHYS        1
80
81 #ifdef CONFIG_PHYS_64BIT
82 #define CONFIG_ADDR_MAP                 1
83 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
84 #endif
85
86 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on */
87 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
88 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
89
90  /*
91   * Config the L2 Cache as L2 SRAM
92   */
93 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
94 #ifdef CONFIG_PHYS_64BIT
95 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8f80000ull
96 #else
97 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
98 #endif
99 #define CONFIG_SYS_L2_SIZE              (512 << 10)
100 #define CONFIG_SYS_INIT_L2_END          (CONFIG_SYS_INIT_L2_ADDR \
101                                         + CONFIG_SYS_L2_SIZE)
102
103 #define CONFIG_SYS_CCSRBAR              0xffe00000
104 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
105
106 /* DDR Setup */
107 #define CONFIG_SYS_FSL_DDR3
108 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
109 #define CONFIG_DDR_SPD
110
111 #define CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
114
115 #define CONFIG_SYS_SDRAM_SIZE           2048ULL /* DDR size on P2020COME */
116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
118
119 #define CONFIG_NUM_DDR_CONTROLLERS      1
120 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
121 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
122
123 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
124 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
125 #define CONFIG_SYS_DDR_SBE              0x00ff0000
126
127 #define CONFIG_SYS_SPD_BUS_NUM          1
128 #define SPD_EEPROM_ADDRESS              0x53
129
130 /*
131  * Memory map
132  *
133  * 0x0000_0000  0x7fff_ffff     DDR3                    2G Cacheable
134  * 0x8000_0000  0x9fff_ffff     PCI Express 3 Mem       1G non-cacheable
135  * 0xa000_0000  0xbfff_ffff     PCI Express 2 Mem       1G non-cacheable
136  * 0xc000_0000  0xdfff_ffff     PCI Express 1 Mem       1G non-cacheable
137  * 0xffc1_0000  0xffc1_ffff     PCI Express 3 IO        64K non-cacheable
138  * 0xffc2_0000  0xffc2_ffff     PCI Express 2 IO        64K non-cacheable
139  * 0xffc3_0000  0xffc3_ffff     PCI Express 1 IO        64K non-cacheable
140  *
141  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
142  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
143  */
144
145 /*
146  * Local Bus Definitions
147  */
148
149 /* There is no NOR Flash on P2020COME */
150 #define CONFIG_SYS_NO_FLASH
151
152 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
153 #define CONFIG_HWCONFIG
154
155 #define CONFIG_SYS_INIT_RAM_LOCK        1
156 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
157 #ifdef CONFIG_PHYS_64BIT
158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       CONFIG_SYS_INIT_RAM_ADDR
160 /* the assembler doesn't like typecast */
161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
162         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
163           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
164 #else
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
168 #endif
169 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
170
171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
172                                                 - GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
174
175 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
176 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
177
178 /* Serial Port - controlled on board with jumper J8
179  * open - index 2
180  * shorted - index 1
181  */
182 #define CONFIG_CONS_INDEX               1
183 #define CONFIG_SYS_NS16550
184 #define CONFIG_SYS_NS16550_SERIAL
185 #define CONFIG_SYS_NS16550_REG_SIZE     1
186 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
187
188 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
189
190 #define CONFIG_SYS_BAUDRATE_TABLE   \
191         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
192
193 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
194 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
195
196 /* Use the HUSH parser */
197 #define CONFIG_SYS_HUSH_PARSER
198
199 /*
200  * Pass open firmware flat tree
201  */
202 #define CONFIG_OF_LIBFDT                1
203 #define CONFIG_OF_BOARD_SETUP           1
204 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
205
206 /* new uImage format support */
207 #define CONFIG_FIT                      1
208 #define CONFIG_FIT_VERBOSE              1
209
210 /* I2C */
211 #define CONFIG_SYS_I2C
212 #define CONFIG_SYS_I2C_FSL
213 #define CONFIG_SYS_FSL_I2C_SPEED        400000
214 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
216 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
217 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
218 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
219 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
220
221 /*
222  * I2C2 EEPROM
223  */
224 #define CONFIG_ID_EEPROM
225 #ifdef CONFIG_ID_EEPROM
226 #define CONFIG_SYS_I2C_EEPROM_NXID
227 #endif
228 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
229 #define CONFIG_SYS_I2C_EEPROM_ADDR2     0x18
230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
231 #define CONFIG_SYS_EEPROM_BUS_NUM       0
232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
233
234 /*
235  * eSPI - Enhanced SPI
236  */
237 #define CONFIG_FSL_ESPI
238 #define CONFIG_SPI_FLASH
239 #define CONFIG_SPI_FLASH_STMICRO
240 #define CONFIG_CMD_SF
241 #define CONFIG_SF_DEFAULT_SPEED         10000000
242 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
243
244 /*
245  * General PCI
246  * Memory space is mapped 1-1, but I/O space must start from 0.
247  */
248 #if defined(CONFIG_PCI)
249
250 /* controller 3, Slot 3, tgtid 3, Base address 8000 */
251 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
252 #define CONFIG_SYS_PCIE3_MEM_BUS        0x80000000
253 #define CONFIG_SYS_PCIE3_MEM_PHYS       0x80000000
254 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000  /* 512M */
255 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc10000
256 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
257 #define CONFIG_SYS_PCIE3_IO_PHYS        0xffc10000
258 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000  /* 64k */
259
260 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
261 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
262 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
263 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
264 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000  /* 512M */
265 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc20000
266 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
267 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc20000
268 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000  /* 64k */
269
270 /* controller 1, Slot 1, tgtid 1, Base address a000 */
271 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
272 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
273 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
274 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000  /* 512M */
275 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc30000
276 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
277 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc30000
278 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000  /* 64k */
279
280 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
281
282 #undef CONFIG_EEPRO100
283 #undef CONFIG_TULIP
284 #undef CONFIG_RTL8139
285
286 #ifdef CONFIG_RTL8139
287 /* This macro is used by RTL8139 but not defined in PPC architecture */
288 #define KSEG1ADDR(x)            (x)
289 #define _IO_BASE                0x00000000
290 #endif
291
292 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
293 #define CONFIG_DOS_PARTITION
294
295 #endif  /* CONFIG_PCI */
296
297 #if defined(CONFIG_TSEC_ENET)
298 #define CONFIG_MII              1       /* MII PHY management */
299 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
300 #define CONFIG_TSEC1            1
301 #define CONFIG_TSEC1_NAME       "eTSEC1"
302 #define CONFIG_TSEC2            1
303 #define CONFIG_TSEC2_NAME       "eTSEC2"
304 #define CONFIG_TSEC3            1
305 #define CONFIG_TSEC3_NAME       "eTSEC3"
306
307 #define TSEC1_PHY_ADDR          0
308 #define TSEC2_PHY_ADDR          2
309 #define TSEC3_PHY_ADDR          1
310
311 #undef CONFIG_VSC7385_ENET
312
313 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
314 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
315 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
316
317 #define TSEC1_PHYIDX            0
318 #define TSEC2_PHYIDX            0
319 #define TSEC3_PHYIDX            0
320
321 #define CONFIG_ETHPRIME         "eTSEC1"
322
323 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
324
325 #endif  /* CONFIG_TSEC_ENET */
326
327 /*
328  * Environment
329  */
330 #if defined(CONFIG_RAMBOOT_SDCARD)
331         #define CONFIG_ENV_IS_IN_MMC    1
332         #define CONFIG_FSL_FIXED_MMC_LOCATION
333         #define CONFIG_ENV_SIZE         0x2000
334         #define CONFIG_SYS_MMC_ENV_DEV  0
335 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
336         #define CONFIG_ENV_IS_IN_SPI_FLASH
337         #define CONFIG_ENV_SPI_BUS      0
338         #define CONFIG_ENV_SPI_CS       0
339         #define CONFIG_ENV_SPI_MAX_HZ   10000000
340         #define CONFIG_ENV_SPI_MODE     0
341         #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
342         #define CONFIG_ENV_SECT_SIZE    0x10000
343         #define CONFIG_ENV_SIZE         0x2000
344 #endif
345
346 #define CONFIG_LOADS_ECHO               1
347 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
348
349 /*
350  * Command line configuration.
351  */
352 #include <config_cmd_default.h>
353
354 #define CONFIG_CMD_ELF
355 #define CONFIG_CMD_I2C
356 #define CONFIG_CMD_IRQ
357 #define CONFIG_CMD_MII
358 #define CONFIG_CMD_PING
359 #define CONFIG_CMD_SETEXPR
360 #define CONFIG_CMD_REGINFO
361
362 #if defined(CONFIG_PCI)
363 #define CONFIG_CMD_NET
364 #define CONFIG_CMD_PCI
365 #endif
366
367 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
368
369 #define CONFIG_MMC      1
370
371 #ifdef CONFIG_MMC
372 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
373 #define CONFIG_CMD_MMC
374 #define CONFIG_DOS_PARTITION
375 #define CONFIG_FSL_ESDHC
376 #define CONFIG_GENERIC_MMC
377 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
378 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
379 #endif /* CONFIG_MMC */
380
381 #define CONFIG_HAS_FSL_DR_USB
382 #ifdef CONFIG_HAS_FSL_DR_USB
383 #define CONFIG_USB_EHCI
384
385 #ifdef CONFIG_USB_EHCI
386 #define CONFIG_CMD_USB
387 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
388 #define CONFIG_USB_EHCI_FSL
389 #define CONFIG_USB_STORAGE
390 #endif
391 #endif
392
393 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
394 #define CONFIG_CMD_EXT2
395 #define CONFIG_CMD_FAT
396 #define CONFIG_DOS_PARTITION
397 #endif
398
399 /* Misc Extra Settings */
400 #define CONFIG_CMD_DHCP                 1
401
402 #define CONFIG_CMD_DATE                 1
403 #define CONFIG_RTC_M41T62               1
404 #define CONFIG_SYS_RTC_BUS_NUM          1
405 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
406
407 /*
408  * Miscellaneous configurable options
409  */
410 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
411 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
412 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
413 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
414 #if defined(CONFIG_CMD_KGDB)
415 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
416 #else
417 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
418 #endif
419 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
420                                                 /* Print Buffer Size */
421 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
422 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
423
424 /*
425  * For booting Linux, the board info and command line data
426  * have to be in the first 64 MB of memory, since this is
427  * the maximum mapped by the Linux kernel during initialization.
428  */
429 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)
430 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)
431
432 #if defined(CONFIG_CMD_KGDB)
433 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
434 #endif
435
436 /*
437  * Environment Configuration
438  */
439
440 /* The mac addresses for all ethernet interface */
441 #if defined(CONFIG_TSEC_ENET)
442 #define CONFIG_HAS_ETH0
443 #define CONFIG_HAS_ETH1
444 #define CONFIG_HAS_ETH2
445 #define CONFIG_HAS_ETH3
446 #endif
447
448 #define CONFIG_HOSTNAME         unknown
449 #define CONFIG_ROOTPATH         "/opt/nfsroot"
450 #define CONFIG_BOOTFILE         "uImage"
451 #define CONFIG_UBOOTPATH        u-boot.bin
452
453 /* default location for tftp and bootm */
454 #define CONFIG_LOADADDR         1000000
455
456 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
457 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
458
459 #define CONFIG_BAUDRATE         115200
460
461 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
462         "hwconfig=fsl_ddr:ecc=on\0"                                     \
463         "bootcmd=run sdboot\0"                                          \
464         "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw "                \
465                 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
466                 "$othbootargs; mmcinfo; "                               \
467                 "ext2load mmc 0:2 $loadaddr /boot/$bootfile; "          \
468                 "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; "            \
469                 "bootm $loadaddr - $fdtaddr\0"                          \
470         "sdfatboot=setenv bootargs root=/dev/ram rw "                   \
471                 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
472                 "$othbootargs; mmcinfo; "                               \
473                 "fatload mmc 0:1 $loadaddr $bootfile; "                 \
474                 "fatload mmc 0:1 $fdtaddr $fdtfile; "                   \
475                 "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; "           \
476                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
477         "usbboot=setenv bootargs root=/dev/sda1 rw "                    \
478                 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
479                 "$othbootargs; "                                        \
480                 "usb start; "                                           \
481                 "ext2load usb 0:1 $loadaddr /boot/$bootfile; "          \
482                 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; "            \
483                 "bootm $loadaddr - $fdtaddr\0"                          \
484         "usbfatboot=setenv bootargs root=/dev/ram rw "                  \
485                 "console=$consoledev,$baudrate $othbootargs; "          \
486                 "usb start; "                                           \
487                 "fatload usb 0:2 $loadaddr $bootfile; "                 \
488                 "fatload usb 0:2 $fdtaddr $fdtfile; "                   \
489                 "fatload usb 0:2 $ramdiskaddr $ramdiskfile; "           \
490                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
491         "usbext2boot=setenv bootargs root=/dev/ram rw "                 \
492                 "console=$consoledev,$baudrate $othbootargs; "          \
493                 "usb start; "                                           \
494                 "ext2load usb 0:4 $loadaddr $bootfile; "                \
495                 "ext2load usb 0:4 $fdtaddr $fdtfile; "                  \
496                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; "          \
497                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"               \
498         "upgradespi=sf probe 0; "                                       \
499                 "setenv startaddr 0; "                                  \
500                 "setenv erasesize a0000; "                              \
501                 "tftp 1000000 $tftppath/$uboot_spi; "                   \
502                 "sf erase $startaddr $erasesize; "                      \
503                 "sf write 1000000 $startaddr $filesize; "               \
504                 "sf erase 100000 120000\0"                              \
505         "clearspienv=sf probe 0;sf erase 100000 20000\0"                \
506         "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0"     \
507         "netdev=eth0\0"                                                 \
508         "rootdelaysecond=15\0"                                          \
509         "uboot_nor=u-boot-nor.bin\0"                                    \
510         "uboot_spi=u-boot-p2020.spi\0"                                  \
511         "uboot_sd=u-boot-p2020.bin\0"                                   \
512         "consoledev=ttyS0\0"                                            \
513         "ramdiskaddr=2000000\0"                                         \
514         "ramdiskfile=rootfs-dev.ext2.img\0"                             \
515         "fdtaddr=c00000\0"                                              \
516         "fdtfile=uImage-2.6.32-p2020.dtb\0"                             \
517         "tftppath=p2020\0"
518
519 #define CONFIG_HDBOOT                                                   \
520         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "              \
521         "console=$consoledev,$baudrate $othbootargs;"                   \
522         "usb start;"                                                    \
523         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"                   \
524         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"                     \
525         "bootm $loadaddr - $fdtaddr"
526
527 #define CONFIG_NFSBOOTCOMMAND                                           \
528         "setenv bootargs root=/dev/nfs rw "                             \
529         "nfsroot=$serverip:$rootpath "                                  \
530         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
531         "console=$consoledev,$baudrate $othbootargs;"                   \
532         "tftp $loadaddr $tftppath/$bootfile;"                           \
533         "tftp $fdtaddr $tftppath/$fdtfile;"                             \
534         "bootm $loadaddr - $fdtaddr"
535
536
537 #define CONFIG_RAMBOOTCOMMAND                                           \
538         "setenv bootargs root=/dev/ram rw "                             \
539         "console=$consoledev,$baudrate $othbootargs;"                   \
540         "tftp $ramdiskaddr $tftppath/$ramdiskfile;"                     \
541         "tftp $loadaddr $tftppath/$bootfile;"                           \
542         "tftp $fdtaddr $tftppath/$fdtfile;"                             \
543         "bootm $loadaddr $ramdiskaddr $fdtaddr"
544
545 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
546
547 #endif  /* __CONFIG_H */