2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
33 #ifdef CONFIG_MK_P1011RDB
36 #ifdef CONFIG_MK_P1020RDB
39 #ifdef CONFIG_MK_P2010RDB
42 #ifdef CONFIG_MK_P2020RDB
47 #define CONFIG_NAND_U_BOOT 1
48 #define CONFIG_RAMBOOT_NAND 1
49 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
52 #ifdef CONFIG_MK_SDCARD
53 #define CONFIG_RAMBOOT_SDCARD 1
54 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
57 #ifdef CONFIG_MK_SPIFLASH
58 #define CONFIG_RAMBOOT_SPIFLASH 1
59 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
62 /* High Level Configuration Options */
63 #define CONFIG_BOOKE 1 /* BOOKE */
64 #define CONFIG_E500 1 /* BOOKE e500 family */
65 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
66 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
67 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
68 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
69 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
70 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
71 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
72 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
73 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
74 #define CONFIG_TSEC_ENET /* tsec ethernet support */
75 #define CONFIG_ENV_OVERWRITE
78 extern unsigned long get_board_sys_clk(unsigned long dummy);
80 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
83 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
88 * These can be toggled for performance analysis, otherwise use default.
90 #define CONFIG_L2_CACHE /* toggle L2 cache */
91 #define CONFIG_BTB /* toggle branch predition */
93 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
95 #define CONFIG_ENABLE_36BIT_PHYS 1
97 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
98 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
99 #define CONFIG_PANIC_HANG /* do not reset board on panic */
102 * Config the L2 Cache as L2 SRAM
104 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
108 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
110 #define CONFIG_SYS_L2_SIZE (512 << 10)
111 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
114 * Base addresses -- Note these are effective addresses where the
115 * actual resources get mapped (not physical addresses)
117 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
118 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
120 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
121 /* CONFIG_SYS_IMMR */
123 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
124 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
126 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
129 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
130 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
133 #define CONFIG_FSL_DDR2
134 #undef CONFIG_FSL_DDR_INTERACTIVE
135 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
136 #undef CONFIG_DDR_DLL
138 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
140 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
144 #define CONFIG_NUM_DDR_CONTROLLERS 1
145 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
146 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
148 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
149 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
150 #define CONFIG_SYS_DDR_SBE 0x00FF0000
155 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
156 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
157 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
159 * Localbus cacheable (TBD)
160 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
162 * Localbus non-cacheable
163 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
164 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
165 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
166 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
167 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
171 * Local Bus Definitions
173 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
175 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
177 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
179 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
182 #define CONFIG_SYS_FLASH_QUIET_TEST
183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
187 #undef CONFIG_SYS_FLASH_CHECKSUM
188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
191 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
193 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
194 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
195 #define CONFIG_SYS_RAMBOOT
197 #undef CONFIG_SYS_RAMBOOT
200 #define CONFIG_FLASH_CFI_DRIVER
201 #define CONFIG_SYS_FLASH_CFI
202 #define CONFIG_SYS_FLASH_EMPTY_INFO
203 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
205 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
206 #define CONFIG_HWCONFIG
208 #define CONFIG_SYS_INIT_RAM_LOCK 1
209 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
210 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
212 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
214 - CONFIG_SYS_GBL_DATA_SIZE)
215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
217 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
218 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
220 #ifndef CONFIG_NAND_SPL
221 #define CONFIG_SYS_NAND_BASE 0xffa00000
223 #define CONFIG_SYS_NAND_BASE 0xfff00000
225 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
226 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
227 #define CONFIG_SYS_MAX_NAND_DEVICE 1
228 #define NAND_MAX_CHIPS 1
229 #define CONFIG_MTD_NAND_VERIFY_WRITE
230 #define CONFIG_CMD_NAND 1
231 #define CONFIG_NAND_FSL_ELBC 1
232 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
234 /* NAND boot: 4K NAND loader config */
235 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
236 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
237 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
238 #define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
239 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
240 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
241 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
243 /* NAND flash config */
244 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
245 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
246 | BR_PS_8 /* Port Size = 8 bit */ \
247 | BR_MS_FCM /* MSEL = FCM */ \
250 #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
258 #ifdef CONFIG_RAMBOOT_NAND
259 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
261 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
262 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
264 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
265 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
266 #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
267 #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
270 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
272 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
274 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
275 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
276 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
277 OR_GPCM_EHTR | OR_GPCM_EAD)
279 /* Serial Port - controlled on board with jumper J8
283 #define CONFIG_CONS_INDEX 1
284 #undef CONFIG_SERIAL_SOFTWARE_FIFO
285 #define CONFIG_SYS_NS16550
286 #define CONFIG_SYS_NS16550_SERIAL
287 #define CONFIG_SYS_NS16550_REG_SIZE 1
288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
290 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
291 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
293 #define CONFIG_SYS_BAUDRATE_TABLE \
294 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
296 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
297 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
299 /* Use the HUSH parser */
300 #define CONFIG_SYS_HUSH_PARSER
301 #ifdef CONFIG_SYS_HUSH_PARSER
302 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
306 * Pass open firmware flat tree
308 #define CONFIG_OF_LIBFDT 1
309 #define CONFIG_OF_BOARD_SETUP 1
310 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
312 /* new uImage format support */
314 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
317 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
318 #define CONFIG_HARD_I2C /* I2C with hardware support */
319 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
320 #define CONFIG_I2C_MULTI_BUS
321 #define CONFIG_I2C_CMD_TREE
322 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
323 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
324 #define CONFIG_SYS_I2C_SLAVE 0x7F
325 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
326 #define CONFIG_SYS_I2C_OFFSET 0x3000
327 #define CONFIG_SYS_I2C2_OFFSET 0x3100
332 #define CONFIG_ID_EEPROM
333 #ifdef CONFIG_ID_EEPROM
334 #define CONFIG_SYS_I2C_EEPROM_NXID
336 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
338 #define CONFIG_SYS_EEPROM_BUS_NUM 1
340 #define CONFIG_RTC_DS1337
341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
344 * Memory space is mapped 1-1, but I/O space must start from 0.
347 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
348 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
349 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
350 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
351 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
352 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
353 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
354 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
355 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
357 /* controller 1, Slot 1, tgtid 1, Base address a000 */
358 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
359 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
360 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
361 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
362 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
363 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
364 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
365 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
367 #if defined(CONFIG_PCI)
368 #define CONFIG_NET_MULTI
369 #define CONFIG_PCI_PNP /* do pci plug-and-play */
371 #undef CONFIG_EEPRO100
373 #undef CONFIG_RTL8139
375 #ifdef CONFIG_RTL8139
376 /* This macro is used by RTL8139 but not defined in PPC architecture */
377 #define KSEG1ADDR(x) (x)
378 #define _IO_BASE 0x00000000
382 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
383 #define CONFIG_DOS_PARTITION
385 #endif /* CONFIG_PCI */
387 #if defined(CONFIG_TSEC_ENET)
388 #ifndef CONFIG_NET_MULTI
389 #define CONFIG_NET_MULTI 1
392 #define CONFIG_MII 1 /* MII PHY management */
393 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
394 #define CONFIG_TSEC1 1
395 #define CONFIG_TSEC1_NAME "eTSEC1"
396 #define CONFIG_TSEC2 1
397 #define CONFIG_TSEC2_NAME "eTSEC2"
398 #define CONFIG_TSEC3 1
399 #define CONFIG_TSEC3_NAME "eTSEC3"
401 #define TSEC1_PHY_ADDR 2
402 #define TSEC2_PHY_ADDR 0
403 #define TSEC3_PHY_ADDR 1
405 #define CONFIG_VSC7385_ENET
407 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
408 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
409 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
411 #define TSEC1_PHYIDX 0
412 #define TSEC2_PHYIDX 0
413 #define TSEC3_PHYIDX 0
417 #ifdef CONFIG_VSC7385_ENET
418 /* The size of the VSC7385 firmware image */
419 #define CONFIG_VSC7385_IMAGE_SIZE 8192
422 #define CONFIG_ETHPRIME "eTSEC1"
424 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
425 #endif /* CONFIG_TSEC_ENET */
430 #if defined(CONFIG_SYS_RAMBOOT)
431 #if defined(CONFIG_RAMBOOT_NAND)
432 #define CONFIG_ENV_IS_IN_NAND 1
433 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
434 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
435 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
436 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
438 #define CONFIG_ENV_SIZE 0x2000
441 #define CONFIG_ENV_IS_IN_FLASH 1
442 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
443 #define CONFIG_ENV_ADDR 0xfff80000
445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
447 #define CONFIG_ENV_SIZE 0x2000
448 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
451 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
452 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
455 * Command line configuration.
457 #include <config_cmd_default.h>
459 #define CONFIG_CMD_DATE
460 #define CONFIG_CMD_ELF
461 #define CONFIG_CMD_I2C
462 #define CONFIG_CMD_IRQ
463 #define CONFIG_CMD_MII
464 #define CONFIG_CMD_PING
465 #define CONFIG_CMD_SETEXPR
467 #if defined(CONFIG_PCI)
468 #define CONFIG_CMD_NET
469 #define CONFIG_CMD_PCI
472 #undef CONFIG_WATCHDOG /* watchdog disabled */
477 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
478 #define CONFIG_CMD_MMC
479 #define CONFIG_DOS_PARTITION
480 #define CONFIG_FSL_ESDHC
481 #define CONFIG_GENERIC_MMC
482 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
484 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
488 #define CONFIG_USB_EHCI
490 #ifdef CONFIG_USB_EHCI
491 #define CONFIG_CMD_USB
492 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
493 #define CONFIG_USB_EHCI_FSL
494 #define CONFIG_USB_STORAGE
497 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
498 #define CONFIG_CMD_EXT2
499 #define CONFIG_CMD_FAT
500 #define CONFIG_DOS_PARTITION
504 * Miscellaneous configurable options
506 #define CONFIG_SYS_LONGHELP /* undef to save memory */
507 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
508 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
509 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
510 #if defined(CONFIG_CMD_KGDB)
511 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
513 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
516 /* Print Buffer Size */
517 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
518 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
519 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
522 * For booting Linux, the board info and command line data
523 * have to be in the first 16 MB of memory, since this is
524 * the maximum mapped by the Linux kernel during initialization.
526 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
529 * Internal Definitions
533 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
534 #define BOOTFLAG_WARM 0x02 /* Software reboot */
536 #if defined(CONFIG_CMD_KGDB)
537 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
538 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
542 * Environment Configuration
545 #if defined(CONFIG_TSEC_ENET)
546 #define CONFIG_HAS_ETH0
547 #define CONFIG_HAS_ETH1
548 #define CONFIG_HAS_ETH2
551 #define CONFIG_HOSTNAME P2020RDB
552 #define CONFIG_ROOTPATH /opt/nfsroot
553 #define CONFIG_BOOTFILE uImage
554 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
556 /* default location for tftp and bootm */
557 #define CONFIG_LOADADDR 1000000
559 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
560 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
562 #define CONFIG_BAUDRATE 115200
564 #define CONFIG_EXTRA_ENV_SETTINGS \
566 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
567 "loadaddr=1000000\0" \
568 "bootfile=uImage\0" \
569 "tftpflash=tftpboot $loadaddr $uboot; " \
570 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
571 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
572 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
573 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
574 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
575 "consoledev=ttyS0\0" \
576 "ramdiskaddr=2000000\0" \
577 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
579 "fdtfile=p2020rdb.dtb\0" \
581 "jffs2nor=mtdblock3\0" \
582 "norbootaddr=ef080000\0" \
583 "norfdtaddr=ef040000\0" \
584 "jffs2nand=mtdblock9\0" \
585 "nandbootaddr=100000\0" \
586 "nandfdtaddr=80000\0" \
587 "nandimgsize=400000\0" \
588 "nandfdtsize=80000\0" \
589 "usb_phy_type=ulpi\0" \
590 "vscfw_addr=ef000000\0" \
591 "othbootargs=ramdisk_size=600000\0" \
592 "usbfatboot=setenv bootargs root=/dev/ram rw " \
593 "console=$consoledev,$baudrate $othbootargs; " \
595 "fatload usb 0:2 $loadaddr $bootfile;" \
596 "fatload usb 0:2 $fdtaddr $fdtfile;" \
597 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
598 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
599 "usbext2boot=setenv bootargs root=/dev/ram rw " \
600 "console=$consoledev,$baudrate $othbootargs; " \
602 "ext2load usb 0:4 $loadaddr $bootfile;" \
603 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
604 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
606 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
607 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
608 "bootm $norbootaddr - $norfdtaddr\0" \
609 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
610 "console=$consoledev,$baudrate $othbootargs;" \
611 "nand read 2000000 $nandbootaddr $nandimgsize;" \
612 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
613 "bootm 2000000 - 3000000;\0"
615 #define CONFIG_NFSBOOTCOMMAND \
616 "setenv bootargs root=/dev/nfs rw " \
617 "nfsroot=$serverip:$rootpath " \
618 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $loadaddr $bootfile;" \
621 "tftp $fdtaddr $fdtfile;" \
622 "bootm $loadaddr - $fdtaddr"
624 #define CONFIG_HDBOOT \
625 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
626 "console=$consoledev,$baudrate $othbootargs;" \
628 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
629 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
630 "bootm $loadaddr - $fdtaddr"
632 #define CONFIG_RAMBOOTCOMMAND \
633 "setenv bootargs root=/dev/ram rw " \
634 "console=$consoledev,$baudrate $othbootargs; " \
635 "tftp $ramdiskaddr $ramdiskfile;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr $ramdiskaddr $fdtaddr"
640 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
642 #endif /* __CONFIG_H */