2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
33 /* High Level Configuration Options */
34 #define CONFIG_BOOKE 1 /* BOOKE */
35 #define CONFIG_E500 1 /* BOOKE e500 family */
36 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
37 #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
41 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
42 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
44 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #define CONFIG_ENV_OVERWRITE
49 extern unsigned long get_board_sys_clk(unsigned long dummy);
51 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
54 #if defined(CONFIG_P2020) || defined(CONFIG_P1020)
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_L2_CACHE /* toggle L2 cache */
62 #define CONFIG_BTB /* toggle branch predition */
64 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
66 #define CONFIG_ENABLE_36BIT_PHYS 1
68 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
69 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
70 #define CONFIG_PANIC_HANG /* do not reset board on panic */
73 * Base addresses -- Note these are effective addresses where the
74 * actual resources get mapped (not physical addresses)
76 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
77 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
78 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
82 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
83 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
86 #define CONFIG_FSL_DDR2
87 #undef CONFIG_FSL_DDR_INTERACTIVE
88 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
93 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_NUM_DDR_CONTROLLERS 1
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
101 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
102 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
103 #define CONFIG_SYS_DDR_SBE 0x00FF0000
105 #define CONFIG_SYS_DDR_TLB_START 9
110 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
111 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
112 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
114 * Localbus cacheable (TBD)
115 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
117 * Localbus non-cacheable
118 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
119 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
120 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
121 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
122 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
126 * Local Bus Definitions
128 #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
130 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
132 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
134 #define CONFIG_FLASH_OR_PRELIM 0xff000ff7
136 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
137 #define CONFIG_SYS_FLASH_QUIET_TEST
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
141 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
142 #undef CONFIG_SYS_FLASH_CHECKSUM
143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_EMPTY_INFO
151 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
153 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
155 #define CONFIG_SYS_INIT_RAM_LOCK 1
156 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
157 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
159 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
160 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
161 - CONFIG_SYS_GBL_DATA_SIZE)
162 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
164 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
165 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
167 #define CONFIG_SYS_NAND_BASE 0xffa00000
168 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
169 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
170 #define CONFIG_SYS_MAX_NAND_DEVICE 1
171 #define NAND_MAX_CHIPS 1
172 #define CONFIG_MTD_NAND_VERIFY_WRITE
173 #define CONFIG_CMD_NAND 1
174 #define CONFIG_NAND_FSL_ELBC 1
175 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
177 /* NAND flash config */
178 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
179 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
180 | BR_PS_8 /* Port Size = 8 bit */ \
181 | BR_MS_FCM /* MSEL = FCM */ \
184 #define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
192 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
193 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
194 #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
195 #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
197 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
199 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
201 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
202 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
203 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
204 OR_GPCM_EHTR | OR_GPCM_EAD)
206 /* Serial Port - controlled on board with jumper J8
210 #define CONFIG_CONS_INDEX 1
211 //#define CONFIG_CONS_INDEX 2
212 #undef CONFIG_SERIAL_SOFTWARE_FIFO
213 #define CONFIG_SYS_NS16550
214 #define CONFIG_SYS_NS16550_SERIAL
215 #define CONFIG_SYS_NS16550_REG_SIZE 1
216 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
218 #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
219 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
221 #define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
227 /* Use the HUSH parser */
228 #define CONFIG_SYS_HUSH_PARSER
229 #ifdef CONFIG_SYS_HUSH_PARSER
230 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
234 * Pass open firmware flat tree
236 #define CONFIG_OF_LIBFDT 1
237 #define CONFIG_OF_BOARD_SETUP 1
238 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
240 #define CONFIG_SYS_64BIT_VSPRINTF 1
241 #define CONFIG_SYS_64BIT_STRTOUL 1
243 /* new uImage format support */
245 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
248 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
249 #define CONFIG_HARD_I2C /* I2C with hardware support */
250 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
251 #define CONFIG_I2C_MULTI_BUS
252 #define CONFIG_I2C_CMD_TREE
253 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
254 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
255 #define CONFIG_SYS_I2C_SLAVE 0x7F
256 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
257 #define CONFIG_SYS_I2C_OFFSET 0x3000
258 #define CONFIG_SYS_I2C2_OFFSET 0x3100
263 #define CONFIG_ID_EEPROM
264 #ifdef CONFIG_ID_EEPROM
265 #define CONFIG_SYS_I2C_EEPROM_NXID
267 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
268 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
269 #define CONFIG_SYS_EEPROM_BUS_NUM 1
271 #define CONFIG_RTC_DS1337
272 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
275 * Memory space is mapped 1-1, but I/O space must start from 0.
278 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
279 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
280 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
281 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
282 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
283 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
284 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
285 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
286 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
288 /* controller 1, Slot 1, tgtid 1, Base address a000 */
289 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
290 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
291 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
292 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
293 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
294 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
296 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
298 #if defined(CONFIG_PCI)
299 #define CONFIG_NET_MULTI
300 #define CONFIG_PCI_PNP /* do pci plug-and-play */
302 #undef CONFIG_EEPRO100
304 #undef CONFIG_RTL8139
306 #ifdef CONFIG_RTL8139
307 /* This macro is used by RTL8139 but not defined in PPC architecture */
308 #define KSEG1ADDR(x) (x)
309 #define _IO_BASE 0x00000000
313 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
314 #define CONFIG_DOS_PARTITION
316 #endif /* CONFIG_PCI */
318 #if defined(CONFIG_TSEC_ENET)
319 #ifndef CONFIG_NET_MULTI
320 #define CONFIG_NET_MULTI 1
323 #define CONFIG_MII 1 /* MII PHY management */
324 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
325 #define CONFIG_TSEC1 1
326 #define CONFIG_TSEC1_NAME "eTSEC1"
327 #define CONFIG_TSEC2 1
328 #define CONFIG_TSEC2_NAME "eTSEC2"
329 #define CONFIG_TSEC3 1
330 #define CONFIG_TSEC3_NAME "eTSEC3"
332 #define TSEC1_PHY_ADDR 2
333 #define TSEC2_PHY_ADDR 0
334 #define TSEC3_PHY_ADDR 1
336 #define CONFIG_VSC7385_ENET
338 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
339 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
340 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
342 #define TSEC1_PHYIDX 0
343 #define TSEC2_PHYIDX 0
344 #define TSEC3_PHYIDX 0
348 #ifdef CONFIG_VSC7385_ENET
349 /* The size of the VSC7385 firmware image */
350 #define CONFIG_VSC7385_IMAGE_SIZE 8192
353 #define CONFIG_ETHPRIME "eTSEC1"
355 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
356 #endif /* CONFIG_TSEC_ENET */
361 #define CONFIG_ENV_IS_IN_FLASH 1
362 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
363 #define CONFIG_ENV_ADDR 0xfff80000
365 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
367 #define CONFIG_ENV_SIZE 0x2000
368 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
370 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
371 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
374 * Command line configuration.
376 #include <config_cmd_default.h>
378 #define CONFIG_CMD_DATE
379 #define CONFIG_CMD_ELF
380 #define CONFIG_CMD_I2C
381 #define CONFIG_CMD_IRQ
382 #define CONFIG_CMD_MII
383 #define CONFIG_CMD_PING
384 #define CONFIG_CMD_SETEXPR
386 #if defined(CONFIG_PCI)
387 #define CONFIG_CMD_NET
388 #define CONFIG_CMD_PCI
391 #undef CONFIG_WATCHDOG /* watchdog disabled */
396 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
397 #define CONFIG_CMD_MMC
398 #define CONFIG_DOS_PARTITION
399 #define CONFIG_FSL_ESDHC
400 #define CONFIG_GENERIC_MMC
401 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
403 #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
407 #define CONFIG_USB_EHCI
409 #ifdef CONFIG_USB_EHCI
410 #define CONFIG_CMD_USB
411 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
412 #define CONFIG_USB_EHCI_FSL
413 #define CONFIG_USB_STORAGE
416 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
417 #define CONFIG_CMD_EXT2
418 #define CONFIG_CMD_FAT
419 #define CONFIG_DOS_PARTITION
423 * Miscellaneous configurable options
425 #define CONFIG_SYS_LONGHELP /* undef to save memory */
426 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
427 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
428 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
429 #if defined(CONFIG_CMD_KGDB)
430 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
432 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
434 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
435 /* Print Buffer Size */
436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
437 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
438 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
441 * For booting Linux, the board info and command line data
442 * have to be in the first 16 MB of memory, since this is
443 * the maximum mapped by the Linux kernel during initialization.
445 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
448 * Internal Definitions
452 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
453 #define BOOTFLAG_WARM 0x02 /* Software reboot */
455 #if defined(CONFIG_CMD_KGDB)
456 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
457 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
461 * Environment Configuration
464 #if defined(CONFIG_TSEC_ENET)
465 #define CONFIG_HAS_ETH0
466 #define CONFIG_HAS_ETH1
467 #define CONFIG_HAS_ETH2
470 #define CONFIG_HOSTNAME P2020RDB
471 #define CONFIG_ROOTPATH /opt/nfsroot
472 #define CONFIG_BOOTFILE uImage
473 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
475 /* default location for tftp and bootm */
476 #define CONFIG_LOADADDR 1000000
478 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
479 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
481 #define CONFIG_BAUDRATE 115200
483 #define CONFIG_EXTRA_ENV_SETTINGS \
485 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
486 "loadaddr=1000000\0" \
487 "bootfile=uImage\0" \
488 "tftpflash=tftpboot $loadaddr $uboot; " \
489 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
490 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
491 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
492 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
493 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
494 "consoledev=ttyS0\0" \
495 "ramdiskaddr=2000000\0" \
496 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
498 "fdtfile=p2020rdb.dtb\0" \
500 "jffs2nor=mtdblock3\0" \
501 "norbootaddr=ef080000\0" \
502 "norfdtaddr=ef040000\0" \
503 "jffs2nand=mtdblock9\0" \
504 "nandbootaddr=100000\0" \
505 "nandfdtaddr=80000\0" \
506 "nandimgsize=400000\0" \
507 "nandfdtsize=80000\0" \
508 "usb_phy_type=ulpi\0" \
509 "vscfw_addr=ef000000\0" \
510 "othbootargs=ramdisk_size=600000\0" \
511 "usbfatboot=setenv bootargs root=/dev/ram rw " \
512 "console=$consoledev,$baudrate $othbootargs; " \
514 "fatload usb 0:2 $loadaddr $bootfile;" \
515 "fatload usb 0:2 $fdtaddr $fdtfile;" \
516 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
517 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
518 "usbext2boot=setenv bootargs root=/dev/ram rw " \
519 "console=$consoledev,$baudrate $othbootargs; " \
521 "ext2load usb 0:4 $loadaddr $bootfile;" \
522 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
523 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
524 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
525 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
526 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
527 "bootm $norbootaddr - $norfdtaddr\0" \
528 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "nand read 2000000 $nandbootaddr $nandimgsize;" \
531 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
532 "bootm 2000000 - 3000000;\0"
534 #define CONFIG_NFSBOOTCOMMAND \
535 "setenv bootargs root=/dev/nfs rw " \
536 "nfsroot=$serverip:$rootpath " \
537 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
538 "console=$consoledev,$baudrate $othbootargs;" \
539 "tftp $loadaddr $bootfile;" \
540 "tftp $fdtaddr $fdtfile;" \
541 "bootm $loadaddr - $fdtaddr"
543 #define CONFIG_HDBOOT \
544 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
545 "console=$consoledev,$baudrate $othbootargs;" \
547 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
548 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
549 "bootm $loadaddr - $fdtaddr"
551 #define CONFIG_RAMBOOTCOMMAND \
552 "setenv bootargs root=/dev/ram rw " \
553 "console=$consoledev,$baudrate $othbootargs; " \
554 "tftp $ramdiskaddr $ramdiskfile;" \
555 "tftp $loadaddr $bootfile;" \
556 "tftp $fdtaddr $fdtfile;" \
557 "bootm $loadaddr $ramdiskaddr $fdtaddr"
559 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
561 #endif /* __CONFIG_H */