2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include "../board/freescale/common/ics307_clk.h"
18 #define CONFIG_PHYS_64BIT
21 /* High Level Configuration Options */
22 #define CONFIG_BOOKE /* BOOKE */
23 #define CONFIG_E500 /* BOOKE e500 family */
24 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
26 #define CONFIG_P1022DS
27 #define CONFIG_MP /* support multiple processors */
29 #ifndef CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SYS_TEXT_BASE 0xeff80000
33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
37 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
38 #define CONFIG_PCI /* Enable PCI/PCIE */
39 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
40 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
41 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
43 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
44 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
46 #ifdef CONFIG_PHYS_64BIT
47 #define CONFIG_ENABLE_36BIT_PHYS
48 #define CONFIG_ADDR_MAP
49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
52 #define CONFIG_FSL_LAW /* Use common FSL init code */
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_L2_CACHE
64 #define CONFIG_SYS_MEMTEST_START 0x00000000
65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
67 #define CONFIG_SYS_CCSRBAR 0xffe00000
68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
71 #define CONFIG_DDR_SPD
72 #define CONFIG_VERY_BIG_RAM
73 #define CONFIG_FSL_DDR3
76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
77 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
83 #define CONFIG_NUM_DDR_CONTROLLERS 1
84 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
85 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
87 /* I2C addresses of SPD EEPROMs */
88 #define CONFIG_SYS_SPD_BUS_NUM 1
89 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
94 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
95 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
96 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
98 * Localbus cacheable (TBD)
99 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
101 * Localbus non-cacheable
102 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
103 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
104 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
105 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
106 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
110 * Local Bus Definitions
112 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
116 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
119 #define CONFIG_FLASH_BR_PRELIM \
120 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
121 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
123 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
124 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
126 #define CONFIG_SYS_BR1_PRELIM \
127 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
128 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
130 #define CONFIG_SYS_FLASH_BANKS_LIST \
131 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
132 #define CONFIG_SYS_FLASH_QUIET_TEST
133 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
135 #define CONFIG_SYS_MAX_FLASH_BANKS 2
136 #define CONFIG_SYS_MAX_FLASH_SECT 1024
138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
140 #define CONFIG_FLASH_CFI_DRIVER
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_EMPTY_INFO
144 #define CONFIG_BOARD_EARLY_INIT_F
145 #define CONFIG_BOARD_EARLY_INIT_R
146 #define CONFIG_MISC_INIT_R
147 #define CONFIG_HWCONFIG
149 #define CONFIG_FSL_NGPIXIS
150 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
151 #ifdef CONFIG_PHYS_64BIT
152 #define PIXIS_BASE_PHYS 0xfffdf0000ull
154 #define PIXIS_BASE_PHYS PIXIS_BASE
157 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
158 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
160 #define PIXIS_LBMAP_SWITCH 7
161 #define PIXIS_LBMAP_MASK 0xF0
162 #define PIXIS_LBMAP_ALTBANK 0x20
163 #define PIXIS_ELBC_SPI_MASK 0xc0
164 #define PIXIS_SPI 0x80
166 #define CONFIG_SYS_INIT_RAM_LOCK
167 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
168 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
170 #define CONFIG_SYS_GBL_DATA_OFFSET \
171 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
174 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
175 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
180 #define CONFIG_CONS_INDEX 1
181 #define CONFIG_SYS_NS16550
182 #define CONFIG_SYS_NS16550_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE 1
184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186 #define CONFIG_SYS_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
192 /* Use the HUSH parser */
193 #define CONFIG_SYS_HUSH_PARSER
194 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
197 #define CONFIG_FSL_DIU_FB
199 #ifdef CONFIG_FSL_DIU_FB
200 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
202 #define CONFIG_CMD_BMP
203 #define CONFIG_CFB_CONSOLE
204 #define CONFIG_VIDEO_SW_CURSOR
205 #define CONFIG_VGA_AS_SINGLE_DEVICE
206 #define CONFIG_VIDEO_LOGO
207 #define CONFIG_VIDEO_BMP_LOGO
208 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
210 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
211 * disable empty flash sector detection, which is I/O-intensive.
213 #undef CONFIG_SYS_FLASH_EMPTY_INFO
216 #ifndef CONFIG_FSL_DIU_FB
221 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
223 #define CONFIG_BIOSEMU
224 #define CONFIG_VIDEO_SW_CURSOR
225 #define CONFIG_ATI_RADEON_FB
226 #define CONFIG_VIDEO_LOGO
227 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
228 #define CONFIG_CFB_CONSOLE
229 #define CONFIG_VGA_AS_SINGLE_DEVICE
233 * Pass open firmware flat tree
235 #define CONFIG_OF_LIBFDT
236 #define CONFIG_OF_BOARD_SETUP
237 #define CONFIG_OF_STDOUT_VIA_ALIAS
239 /* new uImage format support */
241 #define CONFIG_FIT_VERBOSE
244 #define CONFIG_FSL_I2C
245 #define CONFIG_HARD_I2C
246 #define CONFIG_I2C_MULTI_BUS
247 #define CONFIG_SYS_I2C_SPEED 400000
248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
249 #define CONFIG_SYS_I2C_SLAVE 0x7F
250 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
251 #define CONFIG_SYS_I2C_OFFSET 0x3000
252 #define CONFIG_SYS_I2C2_OFFSET 0x3100
257 #define CONFIG_ID_EEPROM
258 #define CONFIG_SYS_I2C_EEPROM_NXID
259 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
261 #define CONFIG_SYS_EEPROM_BUS_NUM 1
264 * eSPI - Enhanced SPI
266 #define CONFIG_SPI_FLASH
267 #define CONFIG_SPI_FLASH_SPANSION
269 #define CONFIG_HARD_SPI
270 #define CONFIG_FSL_ESPI
272 #define CONFIG_CMD_SF
273 #define CONFIG_SF_DEFAULT_SPEED 10000000
274 #define CONFIG_SF_DEFAULT_MODE 0
278 * Memory space is mapped 1-1, but I/O space must start from 0.
281 /* controller 1, Slot 2, tgtid 1, Base address a000 */
282 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
283 #ifdef CONFIG_PHYS_64BIT
284 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
285 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
291 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
292 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
296 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
298 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
300 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
301 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
302 #ifdef CONFIG_PHYS_64BIT
303 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
304 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
306 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
307 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
309 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
310 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
311 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
312 #ifdef CONFIG_PHYS_64BIT
313 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
315 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
317 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
319 /* controller 3, Slot 1, tgtid 3, Base address b000 */
320 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
321 #ifdef CONFIG_PHYS_64BIT
322 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
323 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
325 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
326 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
328 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
329 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
330 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
334 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
336 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
339 #define CONFIG_PCI_PNP /* do pci plug-and-play */
340 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
341 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
345 #define CONFIG_LIBATA
346 #define CONFIG_FSL_SATA
347 #define CONFIG_FSL_SATA_V2
349 #define CONFIG_SYS_SATA_MAX_DEVICE 2
351 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
352 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
354 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
355 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
357 #ifdef CONFIG_FSL_SATA
359 #define CONFIG_CMD_SATA
360 #define CONFIG_DOS_PARTITION
361 #define CONFIG_CMD_EXT2
366 #define CONFIG_CMD_MMC
367 #define CONFIG_FSL_ESDHC
368 #define CONFIG_GENERIC_MMC
369 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
372 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
373 #define CONFIG_CMD_EXT2
374 #define CONFIG_CMD_FAT
375 #define CONFIG_DOS_PARTITION
378 #define CONFIG_TSEC_ENET
379 #ifdef CONFIG_TSEC_ENET
381 #define CONFIG_TSECV2
383 #define CONFIG_MII /* MII PHY management */
384 #define CONFIG_TSEC1 1
385 #define CONFIG_TSEC1_NAME "eTSEC1"
386 #define CONFIG_TSEC2 1
387 #define CONFIG_TSEC2_NAME "eTSEC2"
389 #define TSEC1_PHY_ADDR 1
390 #define TSEC2_PHY_ADDR 2
392 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
393 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395 #define TSEC1_PHYIDX 0
396 #define TSEC2_PHYIDX 0
398 #define CONFIG_ETHPRIME "eTSEC1"
400 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
406 #define CONFIG_ENV_IS_IN_FLASH
407 #define CONFIG_ENV_OVERWRITE
408 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
409 #define CONFIG_ENV_SIZE 0x2000
410 #define CONFIG_ENV_SECT_SIZE 0x20000
412 #define CONFIG_LOADS_ECHO
413 #define CONFIG_SYS_LOADS_BAUD_CHANGE
416 * Command line configuration.
418 #include <config_cmd_default.h>
420 #define CONFIG_CMD_ELF
421 #define CONFIG_CMD_ERRATA
422 #define CONFIG_CMD_IRQ
423 #define CONFIG_CMD_I2C
424 #define CONFIG_CMD_MII
425 #define CONFIG_CMD_PING
426 #define CONFIG_CMD_SETEXPR
427 #define CONFIG_CMD_REGINFO
430 #define CONFIG_CMD_PCI
431 #define CONFIG_CMD_NET
437 #define CONFIG_USB_EHCI
439 #ifdef CONFIG_USB_EHCI
440 #define CONFIG_CMD_USB
441 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
442 #define CONFIG_USB_EHCI_FSL
443 #define CONFIG_USB_STORAGE
444 #define CONFIG_CMD_FAT
448 * Miscellaneous configurable options
450 #define CONFIG_SYS_LONGHELP /* undef to save memory */
451 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
452 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
453 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
454 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
455 #ifdef CONFIG_CMD_KGDB
456 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
458 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
460 /* Print Buffer Size */
461 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
462 #define CONFIG_SYS_MAXARGS 16
463 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
464 #define CONFIG_SYS_HZ 1000
467 * For booting Linux, the board info and command line data
468 * have to be in the first 64 MB of memory, since this is
469 * the maximum mapped by the Linux kernel during initialization.
471 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
472 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
474 #ifdef CONFIG_CMD_KGDB
475 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
476 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
480 * Environment Configuration
483 #define CONFIG_HOSTNAME p1022ds
484 #define CONFIG_ROOTPATH /opt/nfsroot
485 #define CONFIG_BOOTFILE uImage
486 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
488 #define CONFIG_LOADADDR 1000000
490 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
491 #define CONFIG_BOOTARGS
493 #define CONFIG_BAUDRATE 115200
495 #define CONFIG_EXTRA_ENV_SETTINGS \
496 "perf_mode=stable\0" \
497 "memctl_intlv_ctl=2\0" \
499 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
500 "tftpflash=tftpboot $loadaddr $uboot; " \
501 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
502 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
503 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
504 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
505 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
506 "consoledev=ttyS0\0" \
507 "ramdiskaddr=2000000\0" \
508 "ramdiskfile=uramdisk\0" \
510 "fdtfile=p1022ds.dtb\0" \
512 "diuregs=md e002c000 1d\0" \
513 "dium=mw e002c01c\0" \
514 "diuerr=md e002c014 1\0" \
515 "hwconfig=esdhc;audclk:12\0"
517 #define CONFIG_HDBOOT \
518 "setenv bootargs root=/dev/$bdev rw " \
519 "console=$consoledev,$baudrate $othbootargs;" \
520 "tftp $loadaddr $bootfile;" \
521 "tftp $fdtaddr $fdtfile;" \
522 "bootm $loadaddr - $fdtaddr"
524 #define CONFIG_NFSBOOTCOMMAND \
525 "setenv bootargs root=/dev/nfs rw " \
526 "nfsroot=$serverip:$rootpath " \
527 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
528 "console=$consoledev,$baudrate $othbootargs;" \
529 "tftp $loadaddr $bootfile;" \
530 "tftp $fdtaddr $fdtfile;" \
531 "bootm $loadaddr - $fdtaddr"
533 #define CONFIG_RAMBOOTCOMMAND \
534 "setenv bootargs root=/dev/ram rw " \
535 "console=$consoledev,$baudrate $othbootargs;" \
536 "tftp $ramdiskaddr $ramdiskfile;" \
537 "tftp $loadaddr $bootfile;" \
538 "tftp $fdtaddr $fdtfile;" \
539 "bootm $loadaddr $ramdiskaddr $fdtaddr"
541 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND