2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/freescale/common/ics307_clk.h"
15 #define CONFIG_SPL_MMC_MINIMAL
16 #define CONFIG_SPL_FLUSH_IMAGE
17 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
18 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
19 #define CONFIG_SPL_PAD_TO 0x20000
20 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
21 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
22 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
23 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
24 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
25 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
26 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
27 #define CONFIG_SPL_MMC_BOOT
28 #ifdef CONFIG_SPL_BUILD
29 #define CONFIG_SPL_COMMON_INIT_DDR
33 #ifdef CONFIG_SPIFLASH
34 #define CONFIG_SPL_SPI_FLASH_MINIMAL
35 #define CONFIG_SPL_FLUSH_IMAGE
36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
37 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
38 #define CONFIG_SPL_PAD_TO 0x20000
39 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
40 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
42 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
43 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
46 #define CONFIG_SPL_SPI_BOOT
47 #ifdef CONFIG_SPL_BUILD
48 #define CONFIG_SPL_COMMON_INIT_DDR
52 #define CONFIG_NAND_FSL_ELBC
53 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
54 #define CONFIG_SYS_NAND_MAX_OOBFREE 5
57 #ifdef CONFIG_TPL_BUILD
58 #define CONFIG_SPL_NAND_BOOT
59 #define CONFIG_SPL_FLUSH_IMAGE
60 #define CONFIG_SPL_NAND_INIT
61 #define CONFIG_SPL_COMMON_INIT_DDR
62 #define CONFIG_SPL_MAX_SIZE (128 << 10)
63 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
65 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
66 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
67 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
68 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
69 #elif defined(CONFIG_SPL_BUILD)
70 #define CONFIG_SPL_INIT_MINIMAL
71 #define CONFIG_SPL_FLUSH_IMAGE
72 #define CONFIG_SPL_TEXT_BASE 0xff800000
73 #define CONFIG_SPL_MAX_SIZE 4096
74 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
75 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
76 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
77 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
79 #define CONFIG_SPL_PAD_TO 0x20000
80 #define CONFIG_TPL_PAD_TO 0x20000
81 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
85 /* High Level Configuration Options */
86 #define CONFIG_MP /* support multiple processors */
88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
89 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
92 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
93 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
94 #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
95 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
96 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
97 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
99 #define CONFIG_ENABLE_36BIT_PHYS
101 #ifdef CONFIG_PHYS_64BIT
102 #define CONFIG_ADDR_MAP
103 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
106 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
107 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
108 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
111 * These can be toggled for performance analysis, otherwise use default.
113 #define CONFIG_L2_CACHE
116 #define CONFIG_SYS_MEMTEST_START 0x00000000
117 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
119 #define CONFIG_SYS_CCSRBAR 0xffe00000
120 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
122 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
124 #ifdef CONFIG_SPL_BUILD
125 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
129 #define CONFIG_DDR_SPD
130 #define CONFIG_VERY_BIG_RAM
132 #ifdef CONFIG_DDR_ECC
133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
140 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
141 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
143 /* I2C addresses of SPD EEPROMs */
144 #define CONFIG_SYS_SPD_BUS_NUM 1
145 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
147 /* These are used when DDR doesn't use SPD. */
148 #define CONFIG_SYS_SDRAM_SIZE 2048
149 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
150 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
151 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
152 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
153 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
154 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
155 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
156 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
157 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
158 #define CONFIG_SYS_DDR_MODE_1 0x00441221
159 #define CONFIG_SYS_DDR_MODE_2 0x00000000
160 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
161 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
162 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
163 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
164 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
165 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
166 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
167 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
168 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
173 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
174 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
175 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
177 * Localbus cacheable (TBD)
178 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
180 * Localbus non-cacheable
181 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
182 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
183 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
184 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
185 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
186 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
190 * Local Bus Definitions
192 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
193 #ifdef CONFIG_PHYS_64BIT
194 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
196 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
199 #define CONFIG_FLASH_BR_PRELIM \
200 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
201 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
204 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
205 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
207 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
208 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
212 #define CONFIG_SYS_FLASH_QUIET_TEST
213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
215 #define CONFIG_SYS_MAX_FLASH_BANKS 1
216 #define CONFIG_SYS_MAX_FLASH_SECT 1024
218 #ifndef CONFIG_SYS_MONITOR_BASE
219 #ifdef CONFIG_SPL_BUILD
220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
222 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
226 #define CONFIG_FLASH_CFI_DRIVER
227 #define CONFIG_SYS_FLASH_CFI
228 #define CONFIG_SYS_FLASH_EMPTY_INFO
231 #if defined(CONFIG_NAND_FSL_ELBC)
232 #define CONFIG_SYS_NAND_BASE 0xff800000
233 #ifdef CONFIG_PHYS_64BIT
234 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
239 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
240 #define CONFIG_SYS_MAX_NAND_DEVICE 1
241 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
242 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
244 /* NAND flash config */
245 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
246 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
247 | BR_PS_8 /* Port Size = 8 bit */ \
248 | BR_MS_FCM /* MSEL = FCM */ \
250 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
251 | OR_FCM_PGS /* Large Page*/ \
259 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
262 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
263 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
266 #endif /* CONFIG_NAND_FSL_ELBC */
268 #define CONFIG_BOARD_EARLY_INIT_R
269 #define CONFIG_MISC_INIT_R
270 #define CONFIG_HWCONFIG
272 #define CONFIG_FSL_NGPIXIS
273 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
274 #ifdef CONFIG_PHYS_64BIT
275 #define PIXIS_BASE_PHYS 0xfffdf0000ull
277 #define PIXIS_BASE_PHYS PIXIS_BASE
280 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
281 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
283 #define PIXIS_LBMAP_SWITCH 7
284 #define PIXIS_LBMAP_MASK 0xF0
285 #define PIXIS_LBMAP_ALTBANK 0x20
286 #define PIXIS_SPD 0x07
287 #define PIXIS_SPD_SYSCLK_MASK 0x07
288 #define PIXIS_ELBC_SPI_MASK 0xc0
289 #define PIXIS_SPI 0x80
291 #define CONFIG_SYS_INIT_RAM_LOCK
292 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
293 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
295 #define CONFIG_SYS_GBL_DATA_OFFSET \
296 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
297 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
299 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
300 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
303 * Config the L2 Cache as L2 SRAM
305 #if defined(CONFIG_SPL_BUILD)
306 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
307 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
308 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
309 #define CONFIG_SYS_L2_SIZE (256 << 10)
310 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
311 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
312 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
313 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
314 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
315 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
316 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
317 #elif defined(CONFIG_NAND)
318 #ifdef CONFIG_TPL_BUILD
319 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
320 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
321 #define CONFIG_SYS_L2_SIZE (256 << 10)
322 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
323 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
324 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
325 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
326 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
327 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
329 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
330 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
331 #define CONFIG_SYS_L2_SIZE (256 << 10)
332 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
333 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
334 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
342 #define CONFIG_CONS_INDEX 1
343 #define CONFIG_SYS_NS16550_SERIAL
344 #define CONFIG_SYS_NS16550_REG_SIZE 1
345 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
346 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
347 #define CONFIG_NS16550_MIN_FUNCTIONS
350 #define CONFIG_SYS_BAUDRATE_TABLE \
351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
354 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
358 #ifdef CONFIG_FSL_DIU_FB
359 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
360 #define CONFIG_VIDEO_LOGO
361 #define CONFIG_VIDEO_BMP_LOGO
362 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
364 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
365 * disable empty flash sector detection, which is I/O-intensive.
367 #undef CONFIG_SYS_FLASH_EMPTY_INFO
370 #ifndef CONFIG_FSL_DIU_FB
374 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
375 #define CONFIG_BIOSEMU
376 #define CONFIG_ATI_RADEON_FB
377 #define CONFIG_VIDEO_LOGO
378 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
382 #define CONFIG_SYS_I2C
383 #define CONFIG_SYS_I2C_FSL
384 #define CONFIG_SYS_FSL_I2C_SPEED 400000
385 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
386 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
387 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
388 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
389 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
390 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
395 #define CONFIG_ID_EEPROM
396 #define CONFIG_SYS_I2C_EEPROM_NXID
397 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
398 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
399 #define CONFIG_SYS_EEPROM_BUS_NUM 1
402 * eSPI - Enhanced SPI
405 #define CONFIG_HARD_SPI
407 #define CONFIG_SF_DEFAULT_SPEED 10000000
408 #define CONFIG_SF_DEFAULT_MODE 0
412 * Memory space is mapped 1-1, but I/O space must start from 0.
415 /* controller 1, Slot 2, tgtid 1, Base address a000 */
416 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
419 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
421 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
422 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
424 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
425 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
426 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
430 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
432 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
434 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
435 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
438 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
440 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
441 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
443 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
444 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
445 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
449 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
451 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
453 /* controller 3, Slot 1, tgtid 3, Base address b000 */
454 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
455 #ifdef CONFIG_PHYS_64BIT
456 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
457 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
459 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
460 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
462 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
463 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
464 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
465 #ifdef CONFIG_PHYS_64BIT
466 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
468 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
470 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
473 #define CONFIG_PCI_INDIRECT_BRIDGE
474 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
478 #define CONFIG_FSL_SATA_V2
480 #define CONFIG_SYS_SATA_MAX_DEVICE 2
482 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
483 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
485 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
486 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
488 #ifdef CONFIG_FSL_SATA
493 #define CONFIG_FSL_ESDHC
494 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
497 #define CONFIG_TSEC_ENET
498 #ifdef CONFIG_TSEC_ENET
500 #define CONFIG_TSECV2
502 #define CONFIG_MII /* MII PHY management */
503 #define CONFIG_TSEC1 1
504 #define CONFIG_TSEC1_NAME "eTSEC1"
505 #define CONFIG_TSEC2 1
506 #define CONFIG_TSEC2_NAME "eTSEC2"
508 #define TSEC1_PHY_ADDR 1
509 #define TSEC2_PHY_ADDR 2
511 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
514 #define TSEC1_PHYIDX 0
515 #define TSEC2_PHYIDX 0
517 #define CONFIG_ETHPRIME "eTSEC1"
521 * Dynamic MTD Partition support with mtdparts
523 #define CONFIG_MTD_DEVICE
524 #define CONFIG_MTD_PARTITIONS
525 #define CONFIG_FLASH_CFI_MTD
530 #ifdef CONFIG_SPIFLASH
531 #define CONFIG_ENV_SPI_BUS 0
532 #define CONFIG_ENV_SPI_CS 0
533 #define CONFIG_ENV_SPI_MAX_HZ 10000000
534 #define CONFIG_ENV_SPI_MODE 0
535 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
536 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
537 #define CONFIG_ENV_SECT_SIZE 0x10000
538 #elif defined(CONFIG_SDCARD)
539 #define CONFIG_FSL_FIXED_MMC_LOCATION
540 #define CONFIG_ENV_SIZE 0x2000
541 #define CONFIG_SYS_MMC_ENV_DEV 0
542 #elif defined(CONFIG_NAND)
543 #ifdef CONFIG_TPL_BUILD
544 #define CONFIG_ENV_SIZE 0x2000
545 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
547 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
549 #define CONFIG_ENV_OFFSET (1024 * 1024)
550 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
551 #elif defined(CONFIG_SYS_RAMBOOT)
552 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
553 #define CONFIG_ENV_SIZE 0x2000
555 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
556 #define CONFIG_ENV_SIZE 0x2000
557 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
560 #define CONFIG_LOADS_ECHO
561 #define CONFIG_SYS_LOADS_BAUD_CHANGE
566 #define CONFIG_HAS_FSL_DR_USB
567 #ifdef CONFIG_HAS_FSL_DR_USB
568 #ifdef CONFIG_USB_EHCI_HCD
569 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
570 #define CONFIG_USB_EHCI_FSL
575 * Miscellaneous configurable options
577 #define CONFIG_SYS_LONGHELP /* undef to save memory */
578 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
579 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
580 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
583 * For booting Linux, the board info and command line data
584 * have to be in the first 64 MB of memory, since this is
585 * the maximum mapped by the Linux kernel during initialization.
587 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
588 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
590 #ifdef CONFIG_CMD_KGDB
591 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
595 * Environment Configuration
598 #define CONFIG_HOSTNAME p1022ds
599 #define CONFIG_ROOTPATH "/opt/nfsroot"
600 #define CONFIG_BOOTFILE "uImage"
601 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
603 #define CONFIG_LOADADDR 1000000
605 #define CONFIG_EXTRA_ENV_SETTINGS \
607 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
608 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
609 "tftpflash=tftpboot $loadaddr $uboot && " \
610 "protect off $ubootaddr +$filesize && " \
611 "erase $ubootaddr +$filesize && " \
612 "cp.b $loadaddr $ubootaddr $filesize && " \
613 "protect on $ubootaddr +$filesize && " \
614 "cmp.b $loadaddr $ubootaddr $filesize\0" \
615 "consoledev=ttyS0\0" \
616 "ramdiskaddr=2000000\0" \
617 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
618 "fdtaddr=1e00000\0" \
619 "fdtfile=p1022ds.dtb\0" \
621 "hwconfig=esdhc;audclk:12\0"
623 #define CONFIG_HDBOOT \
624 "setenv bootargs root=/dev/$bdev rw " \
625 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr - $fdtaddr"
630 #define CONFIG_NFSBOOTCOMMAND \
631 "setenv bootargs root=/dev/nfs rw " \
632 "nfsroot=$serverip:$rootpath " \
633 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
634 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
635 "tftp $loadaddr $bootfile;" \
636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr - $fdtaddr"
639 #define CONFIG_RAMBOOTCOMMAND \
640 "setenv bootargs root=/dev/ram rw " \
641 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
642 "tftp $ramdiskaddr $ramdiskfile;" \
643 "tftp $loadaddr $bootfile;" \
644 "tftp $fdtaddr $fdtfile;" \
645 "bootm $loadaddr $ramdiskaddr $fdtaddr"
647 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND