2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/freescale/common/ics307_clk.h"
15 #define CONFIG_PHYS_64BIT
19 #define CONFIG_RAMBOOT_SDCARD
20 #define CONFIG_SYS_RAMBOOT
21 #define CONFIG_SYS_EXTRA_ENV_RELOC
22 #define CONFIG_SYS_TEXT_BASE 0x11000000
23 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
26 #ifdef CONFIG_SPIFLASH
27 #define CONFIG_RAMBOOT_SPIFLASH
28 #define CONFIG_SYS_RAMBOOT
29 #define CONFIG_SYS_EXTRA_ENV_RELOC
30 #define CONFIG_SYS_TEXT_BASE 0x11000000
31 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
34 #define CONFIG_NAND_FSL_ELBC
38 #define CONFIG_SPL_INIT_MINIMAL
39 #define CONFIG_SPL_SERIAL_SUPPORT
40 #define CONFIG_SPL_NAND_SUPPORT
41 #define CONFIG_SPL_FLUSH_IMAGE
42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
44 #define CONFIG_SYS_TEXT_BASE 0x00201000
45 #define CONFIG_SPL_TEXT_BASE 0xfffff000
46 #define CONFIG_SPL_MAX_SIZE 4096
47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
48 #define CONFIG_SPL_RELOC_STACK 0x00100000
49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
56 /* High Level Configuration Options */
57 #define CONFIG_BOOKE /* BOOKE */
58 #define CONFIG_E500 /* BOOKE e500 family */
59 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
61 #define CONFIG_P1022DS
62 #define CONFIG_MP /* support multiple processors */
64 #ifndef CONFIG_SYS_TEXT_BASE
65 #define CONFIG_SYS_TEXT_BASE 0xeff80000
68 #ifndef CONFIG_RESET_VECTOR_ADDRESS
69 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
72 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
73 #define CONFIG_PCI /* Enable PCI/PCIE */
74 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
75 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
76 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
77 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
78 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
81 #define CONFIG_ENABLE_36BIT_PHYS
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_ADDR_MAP
85 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
88 #define CONFIG_FSL_LAW /* Use common FSL init code */
90 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
91 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
92 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
95 * These can be toggled for performance analysis, otherwise use default.
97 #define CONFIG_L2_CACHE
100 #define CONFIG_SYS_MEMTEST_START 0x00000000
101 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
103 #define CONFIG_SYS_CCSRBAR 0xffe00000
104 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
106 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
108 #ifdef CONFIG_SPL_BUILD
109 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
114 #define CONFIG_DDR_SPD
115 #define CONFIG_VERY_BIG_RAM
116 #define CONFIG_FSL_DDR3
118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
126 #define CONFIG_NUM_DDR_CONTROLLERS 1
127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
128 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
130 /* I2C addresses of SPD EEPROMs */
131 #define CONFIG_SYS_SPD_BUS_NUM 1
132 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
134 /* These are used when DDR doesn't use SPD. */
135 #define CONFIG_SYS_SDRAM_SIZE 2048
136 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
138 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
139 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
140 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
141 #define CONFIG_SYS_DDR_TIMING_3 0x00010000
142 #define CONFIG_SYS_DDR_TIMING_0 0x40110104
143 #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
144 #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
145 #define CONFIG_SYS_DDR_MODE_1 0x00441221
146 #define CONFIG_SYS_DDR_MODE_2 0x00000000
147 #define CONFIG_SYS_DDR_INTERVAL 0x0a280100
148 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
149 #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
150 #define CONFIG_SYS_DDR_CONTROL 0xc7000008
151 #define CONFIG_SYS_DDR_CONTROL_2 0x24401041
152 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
153 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
154 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
155 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
161 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
162 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
163 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
165 * Localbus cacheable (TBD)
166 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
168 * Localbus non-cacheable
169 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
170 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
171 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
172 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
173 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
174 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
178 * Local Bus Definitions
180 #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
181 #ifdef CONFIG_PHYS_64BIT
182 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
184 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
187 #define CONFIG_FLASH_BR_PRELIM \
188 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
189 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
192 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
193 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
195 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
196 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
199 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
200 #define CONFIG_SYS_FLASH_QUIET_TEST
201 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
203 #define CONFIG_SYS_MAX_FLASH_BANKS 1
204 #define CONFIG_SYS_MAX_FLASH_SECT 1024
206 #ifndef CONFIG_SYS_MONITOR_BASE
207 #ifdef CONFIG_SPL_BUILD
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
214 #define CONFIG_FLASH_CFI_DRIVER
215 #define CONFIG_SYS_FLASH_CFI
216 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #if defined(CONFIG_NAND_FSL_ELBC)
220 #define CONFIG_SYS_NAND_BASE 0xff800000
221 #ifdef CONFIG_PHYS_64BIT
222 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
224 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
227 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
228 #define CONFIG_SYS_MAX_NAND_DEVICE 1
229 #define CONFIG_MTD_NAND_VERIFY_WRITE
230 #define CONFIG_CMD_NAND 1
231 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
232 #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
234 /* NAND flash config */
235 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
236 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
237 | BR_PS_8 /* Port Size = 8 bit */ \
238 | BR_MS_FCM /* MSEL = FCM */ \
240 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
241 | OR_FCM_PGS /* Large Page*/ \
249 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
250 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
252 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
253 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
256 #endif /* CONFIG_NAND_FSL_ELBC */
258 #define CONFIG_BOARD_EARLY_INIT_F
259 #define CONFIG_BOARD_EARLY_INIT_R
260 #define CONFIG_MISC_INIT_R
261 #define CONFIG_HWCONFIG
263 #define CONFIG_FSL_NGPIXIS
264 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
265 #ifdef CONFIG_PHYS_64BIT
266 #define PIXIS_BASE_PHYS 0xfffdf0000ull
268 #define PIXIS_BASE_PHYS PIXIS_BASE
271 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
272 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
274 #define PIXIS_LBMAP_SWITCH 7
275 #define PIXIS_LBMAP_MASK 0xF0
276 #define PIXIS_LBMAP_ALTBANK 0x20
277 #define PIXIS_SPD 0x07
278 #define PIXIS_SPD_SYSCLK_MASK 0x07
279 #define PIXIS_ELBC_SPI_MASK 0xc0
280 #define PIXIS_SPI 0x80
282 #define CONFIG_SYS_INIT_RAM_LOCK
283 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
284 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
286 #define CONFIG_SYS_GBL_DATA_OFFSET \
287 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
288 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
290 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
291 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
296 #define CONFIG_CONS_INDEX 1
297 #define CONFIG_SYS_NS16550
298 #define CONFIG_SYS_NS16550_SERIAL
299 #define CONFIG_SYS_NS16550_REG_SIZE 1
300 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
301 #ifdef CONFIG_SPL_BUILD
302 #define CONFIG_NS16550_MIN_FUNCTIONS
305 #define CONFIG_SYS_BAUDRATE_TABLE \
306 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
308 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
309 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
311 /* Use the HUSH parser */
312 #define CONFIG_SYS_HUSH_PARSER
316 #ifdef CONFIG_FSL_DIU_FB
317 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
319 #define CONFIG_CMD_BMP
320 #define CONFIG_CFB_CONSOLE
321 #define CONFIG_VIDEO_SW_CURSOR
322 #define CONFIG_VGA_AS_SINGLE_DEVICE
323 #define CONFIG_VIDEO_LOGO
324 #define CONFIG_VIDEO_BMP_LOGO
325 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
327 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
328 * disable empty flash sector detection, which is I/O-intensive.
330 #undef CONFIG_SYS_FLASH_EMPTY_INFO
333 #ifndef CONFIG_FSL_DIU_FB
337 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
339 #define CONFIG_BIOSEMU
340 #define CONFIG_VIDEO_SW_CURSOR
341 #define CONFIG_ATI_RADEON_FB
342 #define CONFIG_VIDEO_LOGO
343 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
344 #define CONFIG_CFB_CONSOLE
345 #define CONFIG_VGA_AS_SINGLE_DEVICE
349 * Pass open firmware flat tree
351 #define CONFIG_OF_LIBFDT
352 #define CONFIG_OF_BOARD_SETUP
353 #define CONFIG_OF_STDOUT_VIA_ALIAS
355 /* new uImage format support */
357 #define CONFIG_FIT_VERBOSE
360 #define CONFIG_SYS_I2C
361 #define CONFIG_SYS_I2C_FSL
362 #define CONFIG_SYS_FSL_I2C_SPEED 400000
363 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
364 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
365 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
366 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
367 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
368 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
373 #define CONFIG_ID_EEPROM
374 #define CONFIG_SYS_I2C_EEPROM_NXID
375 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
376 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
377 #define CONFIG_SYS_EEPROM_BUS_NUM 1
380 * eSPI - Enhanced SPI
382 #define CONFIG_SPI_FLASH
383 #define CONFIG_SPI_FLASH_SPANSION
385 #define CONFIG_HARD_SPI
386 #define CONFIG_FSL_ESPI
388 #define CONFIG_CMD_SF
389 #define CONFIG_SF_DEFAULT_SPEED 10000000
390 #define CONFIG_SF_DEFAULT_MODE 0
394 * Memory space is mapped 1-1, but I/O space must start from 0.
397 /* controller 1, Slot 2, tgtid 1, Base address a000 */
398 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
403 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
404 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
406 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
407 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
408 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
412 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
416 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
417 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
422 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
425 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
426 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
427 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
431 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
433 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
435 /* controller 3, Slot 1, tgtid 3, Base address b000 */
436 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
439 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
441 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
442 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
444 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
445 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
446 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
447 #ifdef CONFIG_PHYS_64BIT
448 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
450 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
452 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
455 #define CONFIG_PCI_INDIRECT_BRIDGE
456 #define CONFIG_PCI_PNP /* do pci plug-and-play */
457 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
458 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
462 #define CONFIG_LIBATA
463 #define CONFIG_FSL_SATA
464 #define CONFIG_FSL_SATA_V2
466 #define CONFIG_SYS_SATA_MAX_DEVICE 2
468 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
469 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
471 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
472 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
474 #ifdef CONFIG_FSL_SATA
476 #define CONFIG_CMD_SATA
477 #define CONFIG_DOS_PARTITION
478 #define CONFIG_CMD_EXT2
483 #define CONFIG_CMD_MMC
484 #define CONFIG_FSL_ESDHC
485 #define CONFIG_GENERIC_MMC
486 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
489 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
490 #define CONFIG_CMD_EXT2
491 #define CONFIG_CMD_FAT
492 #define CONFIG_DOS_PARTITION
495 #define CONFIG_TSEC_ENET
496 #ifdef CONFIG_TSEC_ENET
498 #define CONFIG_TSECV2
500 #define CONFIG_MII /* MII PHY management */
501 #define CONFIG_TSEC1 1
502 #define CONFIG_TSEC1_NAME "eTSEC1"
503 #define CONFIG_TSEC2 1
504 #define CONFIG_TSEC2_NAME "eTSEC2"
506 #define TSEC1_PHY_ADDR 1
507 #define TSEC2_PHY_ADDR 2
509 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
510 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512 #define TSEC1_PHYIDX 0
513 #define TSEC2_PHYIDX 0
515 #define CONFIG_ETHPRIME "eTSEC1"
517 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
523 #ifdef CONFIG_RAMBOOT_SPIFLASH
524 #define CONFIG_ENV_IS_IN_SPI_FLASH
525 #define CONFIG_ENV_SPI_BUS 0
526 #define CONFIG_ENV_SPI_CS 0
527 #define CONFIG_ENV_SPI_MAX_HZ 10000000
528 #define CONFIG_ENV_SPI_MODE 0
529 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
530 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
531 #define CONFIG_ENV_SECT_SIZE 0x10000
532 #elif defined(CONFIG_RAMBOOT_SDCARD)
533 #define CONFIG_ENV_IS_IN_MMC
534 #define CONFIG_ENV_SIZE 0x2000
535 #define CONFIG_SYS_MMC_ENV_DEV 0
536 #elif defined(CONFIG_NAND)
537 #define CONFIG_ENV_IS_IN_NAND
538 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
539 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
540 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
541 #elif defined(CONFIG_SYS_RAMBOOT)
542 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
543 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
544 #define CONFIG_ENV_SIZE 0x2000
546 #define CONFIG_ENV_IS_IN_FLASH
547 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
548 #define CONFIG_ENV_ADDR 0xfff80000
550 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
552 #define CONFIG_ENV_SIZE 0x2000
553 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
556 #define CONFIG_LOADS_ECHO
557 #define CONFIG_SYS_LOADS_BAUD_CHANGE
560 * Command line configuration.
562 #include <config_cmd_default.h>
564 #define CONFIG_CMD_ELF
565 #define CONFIG_CMD_ERRATA
566 #define CONFIG_CMD_IRQ
567 #define CONFIG_CMD_I2C
568 #define CONFIG_CMD_MII
569 #define CONFIG_CMD_PING
570 #define CONFIG_CMD_SETEXPR
571 #define CONFIG_CMD_REGINFO
574 #define CONFIG_CMD_PCI
575 #define CONFIG_CMD_NET
581 #define CONFIG_HAS_FSL_DR_USB
582 #ifdef CONFIG_HAS_FSL_DR_USB
583 #define CONFIG_USB_EHCI
585 #ifdef CONFIG_USB_EHCI
586 #define CONFIG_CMD_USB
587 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
588 #define CONFIG_USB_EHCI_FSL
589 #define CONFIG_USB_STORAGE
590 #define CONFIG_CMD_FAT
595 * Miscellaneous configurable options
597 #define CONFIG_SYS_LONGHELP /* undef to save memory */
598 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
599 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
600 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
601 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
602 #ifdef CONFIG_CMD_KGDB
603 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
605 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
607 /* Print Buffer Size */
608 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
609 #define CONFIG_SYS_MAXARGS 16
610 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
611 #define CONFIG_SYS_HZ 1000
614 * For booting Linux, the board info and command line data
615 * have to be in the first 64 MB of memory, since this is
616 * the maximum mapped by the Linux kernel during initialization.
618 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
619 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
621 #ifdef CONFIG_CMD_KGDB
622 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
623 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
627 * Environment Configuration
630 #define CONFIG_HOSTNAME p1022ds
631 #define CONFIG_ROOTPATH "/opt/nfsroot"
632 #define CONFIG_BOOTFILE "uImage"
633 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
635 #define CONFIG_LOADADDR 1000000
637 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
639 #define CONFIG_BAUDRATE 115200
641 #define CONFIG_EXTRA_ENV_SETTINGS \
643 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
644 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
645 "tftpflash=tftpboot $loadaddr $uboot && " \
646 "protect off $ubootaddr +$filesize && " \
647 "erase $ubootaddr +$filesize && " \
648 "cp.b $loadaddr $ubootaddr $filesize && " \
649 "protect on $ubootaddr +$filesize && " \
650 "cmp.b $loadaddr $ubootaddr $filesize\0" \
651 "consoledev=ttyS0\0" \
652 "ramdiskaddr=2000000\0" \
653 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
655 "fdtfile=p1022ds.dtb\0" \
657 "hwconfig=esdhc;audclk:12\0"
659 #define CONFIG_HDBOOT \
660 "setenv bootargs root=/dev/$bdev rw " \
661 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
662 "tftp $loadaddr $bootfile;" \
663 "tftp $fdtaddr $fdtfile;" \
664 "bootm $loadaddr - $fdtaddr"
666 #define CONFIG_NFSBOOTCOMMAND \
667 "setenv bootargs root=/dev/nfs rw " \
668 "nfsroot=$serverip:$rootpath " \
669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
670 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
671 "tftp $loadaddr $bootfile;" \
672 "tftp $fdtaddr $fdtfile;" \
673 "bootm $loadaddr - $fdtaddr"
675 #define CONFIG_RAMBOOTCOMMAND \
676 "setenv bootargs root=/dev/ram rw " \
677 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
678 "tftp $ramdiskaddr $ramdiskfile;" \
679 "tftp $loadaddr $bootfile;" \
680 "tftp $fdtaddr $fdtfile;" \
681 "bootm $loadaddr $ramdiskaddr $fdtaddr"
683 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND