2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
15 #include "../board/freescale/common/ics307_clk.h"
18 #define CONFIG_PHYS_64BIT
21 /* High Level Configuration Options */
22 #define CONFIG_BOOKE /* BOOKE */
23 #define CONFIG_E500 /* BOOKE e500 family */
24 #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
26 #define CONFIG_P1022DS
27 #define CONFIG_MP /* support multiple processors */
29 #ifndef CONFIG_SYS_TEXT_BASE
30 #define CONFIG_SYS_TEXT_BASE 0xeff80000
33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
37 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
38 #define CONFIG_PCI /* Enable PCI/PCIE */
39 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
40 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
41 #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
42 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
43 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
44 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
46 #ifdef CONFIG_PHYS_64BIT
47 #define CONFIG_ENABLE_36BIT_PHYS
48 #define CONFIG_ADDR_MAP
49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
52 #define CONFIG_FSL_LAW /* Use common FSL init code */
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_L2_CACHE
64 #define CONFIG_SYS_MEMTEST_START 0x00000000
65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff
68 * Base addresses -- Note these are effective addresses where the
69 * actual resources get mapped (not physical addresses)
71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
72 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
73 #ifdef CONFIG_PHYS_64BIT
74 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
81 #define CONFIG_DDR_SPD
82 #define CONFIG_VERY_BIG_RAM
83 #define CONFIG_FSL_DDR3
86 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
87 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
93 #define CONFIG_NUM_DDR_CONTROLLERS 1
94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
95 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
97 /* I2C addresses of SPD EEPROMs */
98 #define CONFIG_SYS_SPD_BUS_NUM 1
99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
104 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
105 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
106 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
108 * Localbus cacheable (TBD)
109 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
111 * Localbus non-cacheable
112 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
113 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
114 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
115 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
116 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
120 * Local Bus Definitions
122 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
123 #ifdef CONFIG_PHYS_64BIT
124 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
126 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
129 #define CONFIG_FLASH_BR_PRELIM \
130 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
131 #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
133 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
134 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
136 #define CONFIG_SYS_BR1_PRELIM \
137 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
138 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
140 #define CONFIG_SYS_FLASH_BANKS_LIST \
141 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
142 #define CONFIG_SYS_FLASH_QUIET_TEST
143 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
145 #define CONFIG_SYS_MAX_FLASH_BANKS 2
146 #define CONFIG_SYS_MAX_FLASH_SECT 1024
148 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
150 #define CONFIG_FLASH_CFI_DRIVER
151 #define CONFIG_SYS_FLASH_CFI
152 #define CONFIG_SYS_FLASH_EMPTY_INFO
154 #define CONFIG_BOARD_EARLY_INIT_F
155 #define CONFIG_BOARD_EARLY_INIT_R
156 #define CONFIG_MISC_INIT_R
157 #define CONFIG_HWCONFIG
159 #define CONFIG_FSL_NGPIXIS
160 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
161 #ifdef CONFIG_PHYS_64BIT
162 #define PIXIS_BASE_PHYS 0xfffdf0000ull
164 #define PIXIS_BASE_PHYS PIXIS_BASE
167 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
168 #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
170 #define PIXIS_LBMAP_SWITCH 7
171 #define PIXIS_LBMAP_MASK 0xF0
172 #define PIXIS_LBMAP_ALTBANK 0x20
174 #define CONFIG_SYS_INIT_RAM_LOCK
175 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
178 #define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
183 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
188 #define CONFIG_CONS_INDEX 1
189 #define CONFIG_SYS_NS16550
190 #define CONFIG_SYS_NS16550_SERIAL
191 #define CONFIG_SYS_NS16550_REG_SIZE 1
192 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
194 #define CONFIG_SYS_BAUDRATE_TABLE \
195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
200 /* Use the HUSH parser */
201 #define CONFIG_SYS_HUSH_PARSER
202 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
205 #undef CONFIG_FSL_DIU_FB
207 #ifdef CONFIG_FSL_DIU_FB
208 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
210 #define CONFIG_CMD_BMP
211 #define CONFIG_CFB_CONSOLE
212 #define CONFIG_VGA_AS_SINGLE_DEVICE
213 #define CONFIG_VIDEO_LOGO
214 #define CONFIG_VIDEO_BMP_LOGO
215 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
217 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
218 * disable empty flash sector detection, which is I/O-intensive.
220 #undef CONFIG_SYS_FLASH_EMPTY_INFO
224 * Pass open firmware flat tree
226 #define CONFIG_OF_LIBFDT
227 #define CONFIG_OF_BOARD_SETUP
228 #define CONFIG_OF_STDOUT_VIA_ALIAS
230 /* new uImage format support */
232 #define CONFIG_FIT_VERBOSE
235 #define CONFIG_FSL_I2C
236 #define CONFIG_HARD_I2C
237 #define CONFIG_I2C_MULTI_BUS
238 #define CONFIG_SYS_I2C_SPEED 400000
239 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
240 #define CONFIG_SYS_I2C_SLAVE 0x7F
241 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
242 #define CONFIG_SYS_I2C_OFFSET 0x3000
243 #define CONFIG_SYS_I2C2_OFFSET 0x3100
248 #define CONFIG_ID_EEPROM
249 #define CONFIG_SYS_I2C_EEPROM_NXID
250 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
252 #define CONFIG_SYS_EEPROM_BUS_NUM 1
256 * Memory space is mapped 1-1, but I/O space must start from 0.
259 /* controller 1, Slot 2, tgtid 1, Base address a000 */
260 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
263 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
265 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
266 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
268 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
269 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
270 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
271 #ifdef CONFIG_PHYS_64BIT
272 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
274 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
276 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
278 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
279 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
282 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
284 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
285 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
287 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
288 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
289 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
290 #ifdef CONFIG_PHYS_64BIT
291 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
293 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
295 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
297 /* controller 3, Slot 1, tgtid 3, Base address b000 */
298 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
299 #ifdef CONFIG_PHYS_64BIT
300 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
301 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
303 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
304 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
306 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
307 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
308 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
312 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
314 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
317 #define CONFIG_NET_MULTI
318 #define CONFIG_PCI_PNP /* do pci plug-and-play */
319 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
320 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
324 #define CONFIG_LIBATA
325 #define CONFIG_FSL_SATA
326 #define CONFIG_FSL_SATA_V2
328 #define CONFIG_SYS_SATA_MAX_DEVICE 2
330 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
331 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
333 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
334 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
336 #ifdef CONFIG_FSL_SATA
338 #define CONFIG_CMD_SATA
339 #define CONFIG_DOS_PARTITION
340 #define CONFIG_CMD_EXT2
345 #define CONFIG_CMD_MMC
346 #define CONFIG_FSL_ESDHC
347 #define CONFIG_GENERIC_MMC
348 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
351 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
352 #define CONFIG_CMD_EXT2
353 #define CONFIG_CMD_FAT
354 #define CONFIG_DOS_PARTITION
357 #define CONFIG_TSEC_ENET
358 #ifdef CONFIG_TSEC_ENET
360 #define CONFIG_TSECV2
361 #define CONFIG_NET_MULTI
363 #define CONFIG_MII /* MII PHY management */
364 #define CONFIG_TSEC1 1
365 #define CONFIG_TSEC1_NAME "eTSEC1"
366 #define CONFIG_TSEC2 1
367 #define CONFIG_TSEC2_NAME "eTSEC2"
369 #define TSEC1_PHY_ADDR 1
370 #define TSEC2_PHY_ADDR 2
372 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
373 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
375 #define TSEC1_PHYIDX 0
376 #define TSEC2_PHYIDX 0
378 #define CONFIG_ETHPRIME "eTSEC1"
380 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
386 #define CONFIG_ENV_IS_IN_FLASH
387 #define CONFIG_ENV_OVERWRITE
388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
389 #define CONFIG_ENV_SIZE 0x2000
390 #define CONFIG_ENV_SECT_SIZE 0x20000
392 #define CONFIG_LOADS_ECHO
393 #define CONFIG_SYS_LOADS_BAUD_CHANGE
396 * Command line configuration.
398 #include <config_cmd_default.h>
400 #define CONFIG_CMD_ELF
401 #define CONFIG_CMD_ERRATA
402 #define CONFIG_CMD_IRQ
403 #define CONFIG_CMD_I2C
404 #define CONFIG_CMD_MII
405 #define CONFIG_CMD_PING
406 #define CONFIG_CMD_SETEXPR
407 #define CONFIG_CMD_REGINFO
410 #define CONFIG_CMD_PCI
411 #define CONFIG_CMD_NET
417 #define CONFIG_USB_EHCI
419 #ifdef CONFIG_USB_EHCI
420 #define CONFIG_CMD_USB
421 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
422 #define CONFIG_USB_EHCI_FSL
423 #define CONFIG_USB_STORAGE
424 #define CONFIG_CMD_FAT
428 * Miscellaneous configurable options
430 #define CONFIG_SYS_LONGHELP /* undef to save memory */
431 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
432 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
433 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
434 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
435 #ifdef CONFIG_CMD_KGDB
436 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
438 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
440 /* Print Buffer Size */
441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
442 #define CONFIG_SYS_MAXARGS 16
443 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
444 #define CONFIG_SYS_HZ 1000
447 * For booting Linux, the board info and command line data
448 * have to be in the first 16 MB of memory, since this is
449 * the maximum mapped by the Linux kernel during initialization.
451 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
452 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
454 #ifdef CONFIG_CMD_KGDB
455 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
456 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
460 * Environment Configuration
463 #define CONFIG_HOSTNAME p1022ds
464 #define CONFIG_ROOTPATH /opt/nfsroot
465 #define CONFIG_BOOTFILE uImage
466 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
468 #define CONFIG_LOADADDR 1000000
470 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
471 #define CONFIG_BOOTARGS
473 #define CONFIG_BAUDRATE 115200
475 #define CONFIG_EXTRA_ENV_SETTINGS \
476 "perf_mode=stable\0" \
477 "memctl_intlv_ctl=2\0" \
479 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
480 "tftpflash=tftpboot $loadaddr $uboot; " \
481 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
482 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
483 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
484 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
485 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
486 "consoledev=ttyS0\0" \
487 "ramdiskaddr=2000000\0" \
488 "ramdiskfile=uramdisk\0" \
490 "fdtfile=p1022ds.dtb\0" \
492 "diuregs=md e002c000 1d\0" \
493 "dium=mw e002c01c\0" \
494 "diuerr=md e002c014 1\0" \
495 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
498 #define CONFIG_HDBOOT \
499 "setenv bootargs root=/dev/$bdev rw " \
500 "console=$consoledev,$baudrate $othbootargs;" \
501 "tftp $loadaddr $bootfile;" \
502 "tftp $fdtaddr $fdtfile;" \
503 "bootm $loadaddr - $fdtaddr"
505 #define CONFIG_NFSBOOTCOMMAND \
506 "setenv bootargs root=/dev/nfs rw " \
507 "nfsroot=$serverip:$rootpath " \
508 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
509 "console=$consoledev,$baudrate $othbootargs;" \
510 "tftp $loadaddr $bootfile;" \
511 "tftp $fdtaddr $fdtfile;" \
512 "bootm $loadaddr - $fdtaddr"
514 #define CONFIG_RAMBOOTCOMMAND \
515 "setenv bootargs root=/dev/ram rw " \
516 "console=$consoledev,$baudrate $othbootargs;" \
517 "tftp $ramdiskaddr $ramdiskfile;" \
518 "tftp $loadaddr $bootfile;" \
519 "tftp $fdtaddr $fdtfile;" \
520 "bootm $loadaddr $ramdiskaddr $fdtaddr"
522 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND