3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
12 * board/config.h - configuration options, board specific
19 * High Level Configuration Options
23 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
24 #define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
26 #define CONFIG_SYS_TEXT_BASE 0x40000000
28 /*#define CONFIG_VIDEO 1 */
30 #define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
31 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
32 #undef CONFIG_8xx_CONS_SMC2
33 #undef CONFIG_8xx_CONS_NONE
34 #define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
35 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
36 #define CONFIG_BOOTARGS "ramdisk_size=8000 "\
37 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
38 "nfsaddrs=10.77.77.20:10.77.77.250"
39 #define CONFIG_BOOTCOMMAND "bootm 400e0000"
41 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
42 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
43 #undef CONFIG_WATCHDOG /* watchdog disabled, for now */
49 #define CONFIG_BOOTP_SUBNETMASK
50 #define CONFIG_BOOTP_GATEWAY
51 #define CONFIG_BOOTP_HOSTNAME
52 #define CONFIG_BOOTP_BOOTPATH
53 #define CONFIG_BOOTP_BOOTFILESIZE
57 * Command line configuration.
59 #include <config_cmd_default.h>
61 #define CONFIG_CMD_SOURCE
64 /* call various generic functions */
65 #define CONFIG_MISC_INIT_R
68 * Miscellaneous configurable options
70 #define CONFIG_SYS_LONGHELP /* undef to save memory */
71 #if defined(CONFIG_CMD_KGDB)
72 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
74 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
76 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
77 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
78 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
80 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
81 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
83 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
85 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
88 * Low Level Configuration Settings
89 * (address mappings, register initial values, etc.)
90 * You should know what you are doing if you make changes here.
92 /*-----------------------------------------------------------------------
93 * Internal Memory Mapped Register
95 #define CONFIG_SYS_IMMR 0xFFF00000
97 /*-----------------------------------------------------------------------
98 * Definitions for initial stack pointer and data area (in DPRAM)
100 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
101 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
102 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105 /*-----------------------------------------------------------------------
106 * Start addresses for the final memory configuration
107 * (Set up by the startup code)
108 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
110 #define CONFIG_SYS_SDRAM_BASE 0x00000000
111 #define CONFIG_SYS_FLASH_BASE 0x40000000
112 #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
114 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
117 * For booting Linux, the board info and command line data
118 * have to be in the first 8 MB of memory, since this is
119 * the maximum mapped by the Linux kernel during initialization.
121 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
123 /*-----------------------------------------------------------------------
126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
127 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
129 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
130 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
132 #define CONFIG_ENV_IS_IN_FLASH 1
135 #define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
136 #define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE
138 #define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */
139 #define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
142 #define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
143 #define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
144 #define CONFIG_SYS_FLASH_SN_BYTES 8
146 /*-----------------------------------------------------------------------
147 * Cache Configuration
149 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
150 #if defined(CONFIG_CMD_KGDB)
151 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
154 /*-----------------------------------------------------------------------
155 * SYPCR - System Protection Control 11-9
156 * SYPCR can only be written once after reset!
157 *-----------------------------------------------------------------------
158 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
160 #if defined(CONFIG_WATCHDOG)
161 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
162 SYPCR_SWE | SYPCR_SWP)
164 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
167 /*-----------------------------------------------------------------------
168 * SIUMCR - SIU Module Configuration 12-30
169 *-----------------------------------------------------------------------
170 * PCMCIA config., multi-function pin tri-state
172 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00)
174 /*-----------------------------------------------------------------------
175 * TBSCR - Time Base Status and Control 12-16
176 *-----------------------------------------------------------------------
177 * Clear Reference Interrupt Status, Timebase freezing enabled
179 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
181 /*-----------------------------------------------------------------------
182 * RTCSC - Real-Time Clock Status and Control Register 12-18
183 *-----------------------------------------------------------------------
185 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
187 /*-----------------------------------------------------------------------
188 * PISCR - Periodic Interrupt Status and Control 12-23
189 *-----------------------------------------------------------------------
190 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
192 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
194 /*-----------------------------------------------------------------------
195 * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
196 *-----------------------------------------------------------------------
197 * Reset PLL lock status sticky bit, timer expired status bit and timer
198 * interrupt status bit
200 #define MPC8XX_SPEED 66666666L
201 #define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
202 #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
203 #define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
204 #define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
206 /*-----------------------------------------------------------------------
207 * SCCR - System Clock and reset Control Register 5-3
208 *-----------------------------------------------------------------------
209 * Set clock output, timebase and RTC source and divider,
210 * power management and some other internal clocks
212 #define SCCR_MASK SCCR_EBDF11
213 #define CONFIG_SYS_SCCR (SCCR_TBS | \
214 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
215 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
218 /*-----------------------------------------------------------------------
220 *-----------------------------------------------------------------------
223 #define CONFIG_SYS_DER 0
226 * Init Memory Controller:
228 * BR0 and OR0 (FLASH)
231 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
233 /* used to re-map FLASH both when starting from SRAM or FLASH:
234 * restrict access enough to keep SRAM working (if any)
235 * but not too much to meddle with FLASH accesses
237 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
238 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
240 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
241 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
244 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
245 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
246 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
249 * BR1/2 and OR1/2 (SDRAM)
251 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
252 #define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
253 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
255 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
256 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM)
258 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
259 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
260 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM
261 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
263 /* IO and memory mapped stuff */
264 #define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
265 #define NX823_IO_BASE 0xFF000000 /* start of IO */
266 #define GPOUT_OFFSET (3<<16)
267 #define QUART_OFFSET (4<<16)
268 #define VIDAC_OFFSET (5<<16)
269 #define CPLD_OFFSET (6<<16)
270 #define SED1386_OFFSET (7<<16)
273 * BR3 and OR3 (general purpose output latches)
275 #define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
276 #define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI)
277 #define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
278 #define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V)
281 * BR4 and OR4 (QUART)
283 #define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
284 #define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
285 #define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
286 #define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
289 * BR5 and OR5 (Video DAC)
291 #define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
292 #define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
293 #define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
294 #define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
298 * FIXME timing not verified for CPLD
300 #define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
301 #define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
302 #define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
303 #define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
306 * BR7 and OR7 (SED1386)
307 * FIXME timing not verified for SED controller
309 #define SED1386_BASE 0xF7000000
310 #define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
311 #define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
314 * Memory Periodic Timer Prescaler
317 /* periodic timer for refresh */
318 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
320 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
321 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
322 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
324 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
325 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
326 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
329 * MAMR settings for SDRAM
333 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
334 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
335 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
337 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
338 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
339 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
341 #define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
342 #define CONFIG_ETHADDR 00:10:20:30:40:50
343 #define CONFIG_IPADDR 10.77.77.20
344 #define CONFIG_SERVERIP 10.77.77.250
346 #endif /* __CONFIG_H */