3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
35 * High Level Configuration Options
39 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40 #define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
42 /*#define CONFIG_VIDEO 1 */
44 #define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
45 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46 #undef CONFIG_8xx_CONS_SMC2
47 #undef CONFIG_8xx_CONS_NONE
48 #define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
49 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
50 #define CONFIG_BOOTARGS "ramdisk=8000 "\
51 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
52 "nfsaddrs=10.77.77.20:10.77.77.250"
53 #define CONFIG_BOOTCOMMAND "bootm 400e0000"
55 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
56 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
57 #undef CONFIG_WATCHDOG /* watchdog disabled, for now */
58 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
59 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
60 #define CONFIG_AUTOSCRIPT
62 /* call various generic functions */
63 #define CONFIG_MISC_INIT_R
65 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
66 #include <cmd_confdefs.h>
69 * Miscellaneous configurable options
71 #define CFG_LONGHELP /* undef to save memory */
72 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
73 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
74 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
76 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
78 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
79 #define CFG_MAXARGS 16 /* max number of command args */
80 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
82 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
83 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
85 #define CFG_LOAD_ADDR 0x100000 /* default load address */
87 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
89 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
92 * Low Level Configuration Settings
93 * (address mappings, register initial values, etc.)
94 * You should know what you are doing if you make changes here.
96 /*-----------------------------------------------------------------------
97 * Internal Memory Mapped Register
99 #define CFG_IMMR 0xFFF00000
101 /*-----------------------------------------------------------------------
102 * Definitions for initial stack pointer and data area (in DPRAM)
104 #define CFG_INIT_RAM_ADDR CFG_IMMR
105 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
106 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
107 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
108 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
110 /*-----------------------------------------------------------------------
111 * Start addresses for the final memory configuration
112 * (Set up by the startup code)
113 * Please note that CFG_SDRAM_BASE _must_ start at 0
115 #define CFG_SDRAM_BASE 0x00000000
116 #define CFG_FLASH_BASE 0x40000000
117 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
118 #define CFG_MONITOR_BASE CFG_FLASH_BASE
119 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
122 * For booting Linux, the board info and command line data
123 * have to be in the first 8 MB of memory, since this is
124 * the maximum mapped by the Linux kernel during initialization.
126 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
128 /*-----------------------------------------------------------------------
131 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
134 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
137 #define CFG_ENV_IS_IN_FLASH 1
140 #define CFG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
141 #define CFG_ENV_ADDR CFG_MONITOR_BASE
143 #define CFG_ENV_ADDR 0x40020000 /* absolute address for now */
144 #define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
147 #define CFG_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
148 #define CFG_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
149 #define CFG_FLASH_SN_BYTES 8
151 /*-----------------------------------------------------------------------
152 * Cache Configuration
154 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
155 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
156 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
159 /*-----------------------------------------------------------------------
160 * SYPCR - System Protection Control 11-9
161 * SYPCR can only be written once after reset!
162 *-----------------------------------------------------------------------
163 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
165 #if defined(CONFIG_WATCHDOG)
166 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
167 SYPCR_SWE | SYPCR_SWP)
169 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
172 /*-----------------------------------------------------------------------
173 * SIUMCR - SIU Module Configuration 12-30
174 *-----------------------------------------------------------------------
175 * PCMCIA config., multi-function pin tri-state
177 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00)
179 /*-----------------------------------------------------------------------
180 * TBSCR - Time Base Status and Control 12-16
181 *-----------------------------------------------------------------------
182 * Clear Reference Interrupt Status, Timebase freezing enabled
184 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
186 /*-----------------------------------------------------------------------
187 * RTCSC - Real-Time Clock Status and Control Register 12-18
188 *-----------------------------------------------------------------------
190 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
192 /*-----------------------------------------------------------------------
193 * PISCR - Periodic Interrupt Status and Control 12-23
194 *-----------------------------------------------------------------------
195 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
197 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
199 /*-----------------------------------------------------------------------
200 * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
201 *-----------------------------------------------------------------------
202 * Reset PLL lock status sticky bit, timer expired status bit and timer
203 * interrupt status bit
205 #define MPC8XX_SPEED 66666666L
206 #define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
207 #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
208 #define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
209 #define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
211 /*-----------------------------------------------------------------------
212 * SCCR - System Clock and reset Control Register 5-3
213 *-----------------------------------------------------------------------
214 * Set clock output, timebase and RTC source and divider,
215 * power management and some other internal clocks
217 #define SCCR_MASK SCCR_EBDF11
218 #define CFG_SCCR (SCCR_TBS | \
219 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
220 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
223 /*-----------------------------------------------------------------------
225 *-----------------------------------------------------------------------
231 * Init Memory Controller:
233 * BR0 and OR0 (FLASH)
236 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
238 /* used to re-map FLASH both when starting from SRAM or FLASH:
239 * restrict access enough to keep SRAM working (if any)
240 * but not too much to meddle with FLASH accesses
242 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
243 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
245 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
246 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
249 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
250 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
251 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
254 * BR1/2 and OR1/2 (SDRAM)
256 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
257 #define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
258 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
260 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
261 #define CFG_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM)
263 #define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
264 #define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
265 #define CFG_OR2_PRELIM CFG_OR1_PRELIM
266 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
268 /* IO and memory mapped stuff */
269 #define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
270 #define NX823_IO_BASE 0xFF000000 /* start of IO */
271 #define GPOUT_OFFSET (3<<16)
272 #define QUART_OFFSET (4<<16)
273 #define VIDAC_OFFSET (5<<16)
274 #define CPLD_OFFSET (6<<16)
275 #define SED1386_OFFSET (7<<16)
278 * BR3 and OR3 (general purpose output latches)
280 #define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
281 #define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI)
282 #define CFG_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
283 #define CFG_BR3_PRELIM (GPOUT_BASE | BR_V)
286 * BR4 and OR4 (QUART)
288 #define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
289 #define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
290 #define CFG_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
291 #define CFG_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
294 * BR5 and OR5 (Video DAC)
296 #define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
297 #define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
298 #define CFG_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
299 #define CFG_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
303 * FIXME timing not verified for CPLD
305 #define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
306 #define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
307 #define CFG_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
308 #define CFG_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
311 * BR7 and OR7 (SED1386)
312 * FIXME timing not verified for SED controller
314 #define SED1386_BASE 0xF7000000
315 #define CFG_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
316 #define CFG_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
319 * Memory Periodic Timer Prescaler
322 /* periodic timer for refresh */
323 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
325 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
326 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
327 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
329 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
330 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
331 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
334 * MAMR settings for SDRAM
338 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
339 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
342 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
343 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
344 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
348 * Internal Definitions
352 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
353 #define BOOTFLAG_WARM 0x02 /* Software reboot */
355 #define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
356 #define CONFIG_ETHADDR 00:10:20:30:40:50
357 #define CONFIG_IPADDR 10.77.77.20
358 #define CONFIG_SERVERIP 10.77.77.250
360 #endif /* __CONFIG_H */