2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
33 * High Level Configuration Options
37 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
38 #define CONFIG_NETTA 1 /* ...on a NetTA board */
40 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41 #undef CONFIG_8xx_CONS_SMC2
42 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
46 /* #define CONFIG_XIN 10000000 */
47 #define CONFIG_XIN 50000000
48 #define MPC8XX_HZ 120000000
49 /* #define MPC8XX_HZ 100000000 */
50 /* #define MPC8XX_HZ 50000000 */
51 /* #define MPC8XX_HZ 80000000 */
53 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
63 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
65 #undef CONFIG_BOOTARGS
66 #define CONFIG_BOOTCOMMAND \
68 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
69 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
72 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
73 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #define CONFIG_HW_WATCHDOG
78 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
80 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
82 #undef CONFIG_MAC_PARTITION
83 #undef CONFIG_DOS_PARTITION
85 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
87 #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
88 #define FEC_ENET 1 /* eth.c needs it that way... */
89 #undef CFG_DISCOVER_PHY /* do not discover phys */
91 #define CONFIG_RMII 1 /* use RMII interface */
93 #if defined(CONFIG_NETTA_ISDN)
94 #define CONFIG_ETHER_ON_FEC1 1
95 #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */
96 #define CONFIG_FEC1_PHY_NORXERR 1
97 #undef CONFIG_ETHER_ON_FEC2
99 #define CONFIG_ETHER_ON_FEC1 1
100 #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */
101 #define CONFIG_FEC1_PHY_NORXERR 1
102 #define CONFIG_ETHER_ON_FEC2 1
103 #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */
104 #define CONFIG_FEC2_PHY_NORXERR 1
107 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
110 #define CONFIG_POST (CFG_POST_MEMORY | \
113 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
118 CFG_CMD_PCMCIA | CFG_CMD_IDE | CFG_CMD_FAT | \
124 #define CONFIG_BOARD_EARLY_INIT_F 1
125 #define CONFIG_MISC_INIT_R
127 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
128 #include <cmd_confdefs.h>
131 * Miscellaneous configurable options
133 #define CFG_LONGHELP /* undef to save memory */
134 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
136 #define CFG_HUSH_PARSER 1
137 #define CFG_PROMPT_HUSH_PS2 "> "
139 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
140 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
142 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
144 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
145 #define CFG_MAXARGS 16 /* max number of command args */
146 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
148 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
149 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
151 #define CFG_LOAD_ADDR 0x100000 /* default load address */
153 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
155 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
162 /*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
165 #define CFG_IMMR 0xFF000000
167 /*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
170 #define CFG_INIT_RAM_ADDR CFG_IMMR
171 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
172 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
176 /*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CFG_SDRAM_BASE _must_ start at 0
181 #define CFG_SDRAM_BASE 0x00000000
182 #define CFG_FLASH_BASE 0x40000000
184 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
186 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
188 #define CFG_MONITOR_BASE CFG_FLASH_BASE
189 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
196 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
198 /*-----------------------------------------------------------------------
201 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
202 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
204 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
205 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
207 #define CFG_ENV_IS_IN_FLASH 1
208 #define CFG_ENV_SECT_SIZE 0x10000
210 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
211 #define CFG_ENV_OFFSET 0
212 #define CFG_ENV_SIZE 0x4000
214 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
215 #define CFG_ENV_OFFSET_REDUND 0
216 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
218 /*-----------------------------------------------------------------------
219 * Cache Configuration
221 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
222 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
223 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
226 /*-----------------------------------------------------------------------
227 * SYPCR - System Protection Control 11-9
228 * SYPCR can only be written once after reset!
229 *-----------------------------------------------------------------------
230 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
232 #if defined(CONFIG_WATCHDOG)
233 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
234 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
236 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
239 /*-----------------------------------------------------------------------
240 * SIUMCR - SIU Module Configuration 11-6
241 *-----------------------------------------------------------------------
242 * PCMCIA config., multi-function pin tri-state
244 #ifndef CONFIG_CAN_DRIVER
245 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
246 #else /* we must activate GPL5 in the SIUMCR for CAN */
247 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
248 #endif /* CONFIG_CAN_DRIVER */
250 /*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
255 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
257 /*-----------------------------------------------------------------------
258 * RTCSC - Real-Time Clock Status and Control Register 11-27
259 *-----------------------------------------------------------------------
261 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
263 /*-----------------------------------------------------------------------
264 * PISCR - Periodic Interrupt Status and Control 11-31
265 *-----------------------------------------------------------------------
266 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
268 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
270 /*-----------------------------------------------------------------------
271 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
272 *-----------------------------------------------------------------------
273 * Reset PLL lock status sticky bit, timer expired status bit and timer
274 * interrupt status bit
278 #if CONFIG_XIN == 10000000
280 #if MPC8XX_HZ == 120000000
281 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
282 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
284 #elif MPC8XX_HZ == 100000000
285 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
286 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
288 #elif MPC8XX_HZ == 50000000
289 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
290 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
292 #elif MPC8XX_HZ == 25000000
293 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
294 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
296 #elif MPC8XX_HZ == 40000000
297 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
298 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
300 #elif MPC8XX_HZ == 75000000
301 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
302 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
305 #error unsupported CPU freq for XIN = 10MHz
308 #elif CONFIG_XIN == 50000000
310 #if MPC8XX_HZ == 120000000
311 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
312 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
314 #elif MPC8XX_HZ == 100000000
315 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
316 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
318 #elif MPC8XX_HZ == 80000000
319 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
320 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
322 #elif MPC8XX_HZ == 50000000
323 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
324 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
327 #error unsupported CPU freq for XIN = 50MHz
332 #error unsupported XIN freq
337 *-----------------------------------------------------------------------
338 * SCCR - System Clock and reset Control Register 15-27
339 *-----------------------------------------------------------------------
340 * Set clock output, timebase and RTC source and divider,
341 * power management and some other internal clocks
344 #define SCCR_MASK SCCR_EBDF11
345 #if MPC8XX_HZ > 66666666
346 #define CFG_SCCR (SCCR_TBS | \
347 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
348 SCCR_DFNL001 | SCCR_DFNH000 | SCCR_DFLCD000 | \
349 SCCR_DFALCD00 | SCCR_EBDF01)
351 #define CFG_SCCR (SCCR_TBS | \
352 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
353 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
357 /*-----------------------------------------------------------------------
359 *-----------------------------------------------------------------------
362 /*#define CFG_DER 0x2002000F*/
366 * Init Memory Controller:
368 * BR0/1 and OR0/1 (FLASH)
371 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
373 /* used to re-map FLASH both when starting from SRAM or FLASH:
374 * restrict access enough to keep SRAM working (if any)
375 * but not too much to meddle with FLASH accesses
377 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
378 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
380 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
381 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
383 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
384 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
385 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
388 * BR3 and OR3 (SDRAM)
391 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
392 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
394 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
395 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
397 #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
398 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
401 * Memory Periodic Timer Prescaler
405 * Memory Periodic Timer Prescaler
407 * The Divider for PTA (refresh timer) configuration is based on an
408 * example SDRAM configuration (64 MBit, one bank). The adjustment to
409 * the number of chip selects (NCS) and the actually needed refresh
410 * rate is done by setting MPTPR.
412 * PTA is calculated from
413 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 * gclk CPU clock (not bus clock!)
416 * Trefresh Refresh cycle * 4 (four word bursts used)
418 * 4096 Rows from SDRAM example configuration
419 * 1000 factor s -> ms
420 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
421 * 4 Number of refresh cycles per period
422 * 64 Refresh cycle in ms per number of rows
423 * --------------------------------------------
424 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 * 50 MHz => 50.000.000 / Divider = 98
427 * 66 Mhz => 66.000.000 / Divider = 129
428 * 80 Mhz => 80.000.000 / Divider = 156
431 #if MPC8XX_HZ == 120000000
432 #define CFG_MAMR_PTA 234
433 #elif MPC8XX_HZ == 100000000
434 #define CFG_MAMR_PTA 195
435 #elif MPC8XX_HZ == 80000000
436 #define CFG_MAMR_PTA 156
437 #elif MPC8XX_HZ == 50000000
438 #define CFG_MAMR_PTA 98
440 #error Unknown frequency
445 * For 16 MBit, refresh rates could be 31.3 us
446 * (= 64 ms / 2K = 125 / quad bursts).
447 * For a simpler initialization, 15.6 us is used instead.
449 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
450 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
452 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
453 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
455 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
456 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
457 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
460 * MAMR settings for SDRAM
464 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
470 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474 * Internal Definitions
478 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
479 #define BOOTFLAG_WARM 0x02 /* Software reboot */
481 #define CONFIG_ARTOS /* include ARTOS support */
483 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
485 /***********************************************************************************************************
489 +------+----------------+--------+------------------------------------------------------------
490 | # | Name | Type | Comment
491 +------+----------------+--------+------------------------------------------------------------
492 | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK
493 | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK)
494 | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA
495 | PA7 | DCL1_3V | Periph | IDL1 PCM clock
496 | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx
497 | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx
498 | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA
499 | PA12 | P_SHDN | Output | TPS2211A PCMCIA
500 | PA13 | ETH_LOOP | Output | CISCO Loopback remote power
501 | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
502 | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA
503 | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA
504 | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board
505 | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only)
506 | PB16 | DREQ1 | Output | D channel request for S-interface chip 1.
507 | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC
508 | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC
509 | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only)
510 | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom
511 | PB21 | LEDIO | Output | Led mode indication for PHY
512 | PB22 | UART_CTS | Input | UART CTS
513 | PB23 | UART_RTS | Output | UART RTS
514 | PB24 | UART_RX | Periph | UART Data Rx
515 | PB25 | UART_TX | Periph | UART Data Tx
516 | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock)
517 | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data)
518 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
519 | PB29 | SPI_TXD | Output | SPI Data Tx
520 | PB30 | SPI_CLK | Output | SPI Clock
521 | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1
522 | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt)
523 | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt)
524 | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
525 | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt)
526 | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
527 | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt)
528 | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt)
529 | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt)
530 | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt)
531 | PC13 | F_RY_BY | Input | NAND ready signal (interrupt)
532 | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK)
533 | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request.
534 | PD3 | F_ALE | Output | NAND
535 | PD4 | F_CLE | Output | NAND
536 | PD5 | F_CE | Output | NAND
537 | PD6 | DSP_INT | Output | DSP debug interrupt
538 | PD7 | DSP_RESET | Output | DSP reset
539 | PD8 | RMII_MDC | Periph | MII mgt clock
540 | PD9 | SPIEN_C1 | Output | SPI CS for codec #1
541 | PD10 | SPIEN_C2 | Output | SPI CS for codec #2
542 | PD11 | SPIEN_C3 | Output | SPI CS for codec #3
543 | PD12 | FSC2 | Periph | IDL2 frame sync
544 | PD13 | DGRANT2 | Input | D channel grant from S #2
545 | PD14 | SPIEN_C4 | Output | SPI CS for codec #4
546 | PD15 | TP700 | Output | Testpoint for software debugging
547 | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data
548 | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data
549 | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for
550 | | DCL2 | Periph | NetRoute: PCM clock #2
551 | PE17 | TP703 | Output | Testpoint for software debugging
552 | PE18 | DGRANT1 | Input | D channel grant from S #1
553 | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable
554 | | PCM2OUT | Periph | NetRoute: Tx data for IDL2
555 | PE20 | FSC1 | Periph | IDL1 frame sync
556 | PE21 | RMII2-RXD0 | Periph | FEC2 receive data
557 | PE22 | RMII2-RXD1 | Periph | FEC2 receive data
558 | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC
559 | PE24 | U-N1 | Output | Select user/network for S #1 (0=user)
560 | PE25 | U-N2 | Output | Select user/network for S #2 (0=user)
561 | PE26 | RMII2-RXDV | Periph | FEC2 valid
562 | PE27 | DREQ2 | Output | D channel request for S #2.
563 | PE28 | FPGA_DONE | Input | FPGA done signal
564 | PE29 | FPGA_INIT | Output | FPGA init signal
565 | PE30 | UDOUT2_3V | Input | IDL2 PCM input
567 +------+----------------+--------+---------------------------------------------------
571 +------+----------------+------------------------------------------------------------
573 +------+----------------+------------------------------------------------------------
574 | CS0 | CS0 | Boot flash
575 | CS1 | CS_FLASH | NAND flash
577 | CS3 | DCS_DRAM | DRAM
578 | CS4 | CS_ER1 | External output register
579 +------+----------------+------------------------------------------------------------
583 +------+----------------+------------------------------------------------------------
585 +------+----------------+------------------------------------------------------------
586 | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
587 | IRQ3 | IRQ_DSP | DSP interrupt
588 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
589 +------+----------------+------------------------------------------------------------
591 *************************************************************************************************/
593 #define DSP_SIZE 0x00010000 /* 64K */
594 #define NAND_SIZE 0x00010000 /* 64K */
595 #define ER_SIZE 0x00010000 /* 64K */
596 #define DUMMY_SIZE 0x00010000 /* 64K */
598 #define DSP_BASE 0xF1000000
599 #define NAND_BASE 0xF1010000
600 #define ER_BASE 0xF1020000
601 #define DUMMY_BASE 0xF1FF0000
603 /****************************************************************/
606 #define CFG_NAND_BASE NAND_BASE
607 #define CONFIG_MTD_NAND_ECC_JFFS2
609 #define CFG_MAX_NAND_DEVICE 1
612 #define SECTORSIZE 512
613 #define ADDR_COLUMN 1
615 #define ADDR_COLUMN_PAGE 3
616 #define NAND_ChipID_UNKNOWN 0x00
617 #define NAND_MAX_FLOORS 1
618 #define NAND_MAX_CHIPS 1
620 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
621 #define NAND_DISABLE_CE(nand) \
623 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
626 #define NAND_ENABLE_CE(nand) \
628 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
631 #define NAND_CTL_CLRALE(nandptr) \
633 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
636 #define NAND_CTL_SETALE(nandptr) \
638 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
641 #define NAND_CTL_CLRCLE(nandptr) \
643 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
646 #define NAND_CTL_SETCLE(nandptr) \
648 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
652 #define NAND_WAIT_READY(nand) \
654 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
659 #define NAND_WAIT_READY(nand) udelay(12)
662 #define WRITE_NAND_COMMAND(d, adr) \
664 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
667 #define WRITE_NAND_ADDRESS(d, adr) \
669 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
672 #define WRITE_NAND(d, adr) \
674 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
677 #define READ_NAND(adr) \
678 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
680 /*****************************************************************************/
683 /*-----------------------------------------------------------------------
685 *-----------------------------------------------------------------------
688 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
689 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
690 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
691 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
692 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
693 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
694 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
695 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
697 /*-----------------------------------------------------------------------
698 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
699 *-----------------------------------------------------------------------
702 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
704 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
705 #undef CONFIG_IDE_LED /* LED for ide not supported */
706 #undef CONFIG_IDE_RESET /* reset for ide not supported */
708 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
709 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
711 #define CFG_ATA_IDE0_OFFSET 0x0000
713 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
715 /* Offset for data I/O */
716 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
718 /* Offset for normal register accesses */
719 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
721 /* Offset for alternate registers */
722 #define CFG_ATA_ALT_OFFSET 0x0100
724 #define CONFIG_MAC_PARTITION
725 #define CONFIG_DOS_PARTITION
728 /*************************************************************************************************/
730 #define CONFIG_CDP_DEVICE_ID 20
731 #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
732 #define CONFIG_CDP_PORT_ID "eth%d"
733 #define CONFIG_CDP_CAPABILITIES 0x00000010
734 #define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__
735 #define CONFIG_CDP_PLATFORM "Intracom NetTA"
736 #define CONFIG_CDP_TRIGGER 0x20020001
737 #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
738 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */
740 /*************************************************************************************************/
742 #define CONFIG_AUTO_COMPLETE 1
744 /*************************************************************************************************/
746 #define CONFIG_CRC32_VERIFY 1
748 /*************************************************************************************************/
750 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
752 /*************************************************************************************************/
754 #endif /* __CONFIG_H */