2 * Copyright (C) Matrix Vision GmbH 2008
4 * Matrix Vision mvBlueLYNX-M7 configuration file
5 * based on Freescale's MPC8349ITX.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
36 #define CONFIG_MPC83xx 1
37 #define CONFIG_MPC834x 1
38 #define CONFIG_MPC8343 1
40 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
42 #define CONFIG_SYS_IMMR 0xE0000000
45 #define CONFIG_PCI_SKIP_HOST_BRIDGE
46 #define CONFIG_HARD_I2C
47 #define CONFIG_TSEC_ENET
48 #define CONFIG_MPC8XXX_SPI
49 #define CONFIG_HARD_SPI
50 #define MVBLM7_MMC_CS 0x04000000
51 #define CONFIG_MISC_INIT_R
54 #define CONFIG_FSL_I2C
55 #define CONFIG_I2C_MULTI_BUS
56 #define CONFIG_SYS_I2C_OFFSET 0x3000
57 #define CONFIG_SYS_I2C2_OFFSET 0x3100
59 #define CONFIG_SYS_I2C_SPEED 100000
60 #define CONFIG_SYS_I2C_SLAVE 0x7F
65 #undef CONFIG_SPD_EEPROM
67 #define CONFIG_SYS_DDR_BASE 0x00000000
68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
69 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
70 #define CONFIG_SYS_83XX_DDR_USES_CS0 1
71 #define CONFIG_SYS_MEMTEST_START (60<<20)
72 #define CONFIG_SYS_MEMTEST_END (70<<20)
73 #define CONFIG_VERY_BIG_RAM
75 #define CONFIG_SYS_DDRCDR 0x22000001
76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
78 #define CONFIG_SYS_DDR_SIZE 512
80 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
82 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
84 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
85 #define CONFIG_SYS_DDR_TIMING_1 0x3837c322
86 #define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
87 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
89 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
90 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
91 #define CONFIG_SYS_DDR_INTERVAL 0x02000100
93 #define CONFIG_SYS_DDR_MODE 0x04040242
94 #define CONFIG_SYS_DDR_MODE2 0x00800000
97 #define CONFIG_SYS_FLASH_CFI
98 #define CONFIG_FLASH_CFI_DRIVER
99 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
101 #define CONFIG_SYS_FLASH_BASE 0xFF800000
102 #define CONFIG_SYS_FLASH_SIZE 8
103 #define CONFIG_SYS_FLASH_SIZE_SHIFT 3
104 #define CONFIG_SYS_FLASH_EMPTY_INFO
105 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
106 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
107 #define CONFIG_SYS_MAX_FLASH_BANKS 1
108 #define CONFIG_SYS_MAX_FLASH_SECT 256
110 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
111 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
120 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
121 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \
122 | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
125 * U-Boot memory configuration
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
128 #undef CONFIG_SYS_RAMBOOT
130 #define CONFIG_SYS_INIT_RAM_LOCK
131 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
132 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
134 #define CONFIG_SYS_GBL_DATA_OFFSET \
135 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
136 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
138 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
139 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
140 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
143 * Local Bus LCRR and LBCR regs
144 * LCRR: DLL bypass, Clock divider is 4
145 * External Local Bus rate is
146 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
148 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
149 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
150 #define CONFIG_SYS_LBC_LBCR 0x00000000
152 /* LB sdram refresh timer, about 6us */
153 #define CONFIG_SYS_LBC_LSRT 0x32000000
154 /* LB refresh timer prescal, 266MHz/32*/
155 #define CONFIG_SYS_LBC_MRTPR 0x20000000
160 #define CONFIG_CONS_INDEX 1
161 #define CONFIG_SYS_NS16550
162 #define CONFIG_SYS_NS16550_SERIAL
163 #define CONFIG_SYS_NS16550_REG_SIZE 1
164 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
166 #define CONFIG_SYS_BAUDRATE_TABLE \
167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
169 #define CONFIG_CONSOLE ttyS0
170 #define CONFIG_BAUDRATE 115200
172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
175 /* pass open firmware flat tree */
176 #define CONFIG_OF_LIBFDT 1
177 #define CONFIG_OF_BOARD_SETUP 1
178 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
179 #define MV_DTB_NAME "mvblm7.dtb"
184 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
185 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
186 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
187 #define CONFIG_SYS_PCI1_MMIO_BASE \
188 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
189 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
190 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
191 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
192 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
193 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
195 #define CONFIG_NET_RETRY_COUNT 3
197 #define CONFIG_PCI_66M
198 #define CONFIG_83XX_CLKIN 66666667
199 #define CONFIG_PCI_PNP
200 #define CONFIG_PCI_SCAN_SHOW
204 #define CONFIG_SYS_VSC8601_SKEWFIX
205 #define CONFIG_SYS_VSC8601_SKEW_TX 3
206 #define CONFIG_SYS_VSC8601_SKEW_RX 3
211 #define CONFIG_HAS_ETH0
212 #define CONFIG_TSEC1_NAME "TSEC0"
213 #define CONFIG_FEC1_PHY_NORXERR
214 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
215 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
216 #define TSEC1_PHY_ADDR 0x10
217 #define TSEC1_PHYIDX 0
218 #define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
220 #define CONFIG_HAS_ETH1
221 #define CONFIG_TSEC2_NAME "TSEC1"
222 #define CONFIG_FEC2_PHY_NORXERR
223 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
224 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
225 #define TSEC2_PHY_ADDR 0x11
226 #define TSEC2_PHYIDX 0
227 #define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
229 #define CONFIG_ETHPRIME "TSEC0"
231 #define CONFIG_BOOTP_VENDOREX
232 #define CONFIG_BOOTP_SUBNETMASK
233 #define CONFIG_BOOTP_GATEWAY
234 #define CONFIG_BOOTP_DNS
235 #define CONFIG_BOOTP_DNS2
236 #define CONFIG_BOOTP_HOSTNAME
237 #define CONFIG_BOOTP_BOOTFILESIZE
238 #define CONFIG_BOOTP_BOOTPATH
239 #define CONFIG_BOOTP_NTPSERVER
240 #define CONFIG_BOOTP_RANDOM_DELAY
241 #define CONFIG_BOOTP_SEND_HOSTNAME
244 #define CONFIG_SYS_USB_HOST
245 #define CONFIG_USB_EHCI
246 #define CONFIG_USB_EHCI_FSL
247 #define CONFIG_HAS_FSL_DR_USB
248 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
253 #undef CONFIG_SYS_FLASH_PROTECTION
254 #define CONFIG_ENV_OVERWRITE
256 #define CONFIG_ENV_IS_IN_FLASH 1
257 #define CONFIG_ENV_ADDR 0xFF800000
258 #define CONFIG_ENV_SIZE 0x2000
259 #define CONFIG_ENV_SECT_SIZE 0x2000
260 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
261 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
263 #define CONFIG_LOADS_ECHO
264 #define CONFIG_SYS_LOADS_BAUD_CHANGE
267 * Command line configuration.
269 #include <config_cmd_default.h>
271 #define CONFIG_CMD_CACHE
272 #define CONFIG_CMD_IRQ
273 #define CONFIG_CMD_NET
274 #define CONFIG_CMD_MII
275 #define CONFIG_CMD_PING
276 #define CONFIG_CMD_DHCP
277 #define CONFIG_CMD_SDRAM
278 #define CONFIG_CMD_PCI
279 #define CONFIG_CMD_I2C
280 #define CONFIG_CMD_FPGA
281 #define CONFIG_CMD_USB
282 #define CONFIG_DOS_PARTITION
284 #undef CONFIG_WATCHDOG
287 * Miscellaneous configurable options
289 #define CONFIG_SYS_LONGHELP
290 #define CONFIG_CMDLINE_EDITING
291 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
292 #define CONFIG_SYS_HUSH_PARSER
293 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
295 /* default load address */
296 #define CONFIG_SYS_LOAD_ADDR 0x2000000
297 /* default location for tftp and bootm */
298 #define CONFIG_LOADADDR 0x200000
300 #define CONFIG_SYS_PROMPT "mvBL-M7> "
301 #define CONFIG_SYS_CBSIZE 256
303 #define CONFIG_SYS_PBSIZE \
304 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
305 #define CONFIG_SYS_MAXARGS 16
306 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
307 #define CONFIG_SYS_HZ 1000
310 * For booting Linux, the board info and command line data
311 * have to be in the first 256 MB of memory, since this is
312 * the maximum mapped by the Linux kernel during initialization.
314 /* Initial Memory map for Linux*/
315 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
317 #define CONFIG_SYS_HRCW_LOW 0x0
318 #define CONFIG_SYS_HRCW_HIGH 0x0
323 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
324 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
325 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
326 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
329 #define CONFIG_SYS_SCCR_ENCCM 0
330 #define CONFIG_SYS_SCCR_USBMPHCM 0
331 #define CONFIG_SYS_SCCR_USBDRCM 2
332 #define CONFIG_SYS_SCCR_TSEC1CM 1
333 #define CONFIG_SYS_SCCR_TSEC2CM 1
335 #define CONFIG_SYS_SICRH 0x1fef0003
336 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
338 #define CONFIG_SYS_HID0_INIT 0x000000000
339 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
340 HID0_ENABLE_INSTRUCTION_CACHE)
342 #define CONFIG_SYS_HID2 HID2_HBE
343 #define CONFIG_HIGH_BATS 1
346 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
349 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
355 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
358 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
362 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
364 | BATL_CACHEINHIBIT \
365 | BATL_GUARDEDSTORAGE)
366 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
372 #define CONFIG_SYS_IBAT3L 0
373 #define CONFIG_SYS_IBAT3U 0
374 #define CONFIG_SYS_IBAT4L 0
375 #define CONFIG_SYS_IBAT4U 0
377 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
378 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
380 | BATL_CACHEINHIBIT \
381 | BATL_GUARDEDSTORAGE)
382 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
387 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
388 #define CONFIG_SYS_IBAT6L (0xF0000000 \
390 | BATL_MEMCOHERENCE \
393 #define CONFIG_SYS_IBAT6U (0xF0000000 \
397 #define CONFIG_SYS_IBAT7L 0
398 #define CONFIG_SYS_IBAT7U 0
400 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
401 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
402 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
403 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
404 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
405 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
406 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
407 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
408 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
409 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
410 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
411 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
412 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
413 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
414 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
415 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
418 * Environment Configuration
420 #define CONFIG_ENV_OVERWRITE
422 #define CONFIG_NETDEV eth0
424 /* Default path and filenames */
425 #define CONFIG_BOOTDELAY 5
426 #define CONFIG_AUTOBOOT_KEYED
427 #define CONFIG_AUTOBOOT_STOP_STR "s"
428 #define CONFIG_ZERO_BOOTDELAY_CHECK
429 #define CONFIG_RESET_TO_RETRY 1000
431 #define MV_CI "mvBL-M7"
432 #define MV_VCI "mvBL-M7"
433 #define MV_FPGA_DATA 0xfff40000
434 #define MV_FPGA_SIZE 0
435 #define MV_KERNEL_ADDR 0xff810000
436 #define MV_INITRD_ADDR 0xffb00000
437 #define MV_SCRIPT_ADDR 0xff804000
438 #define MV_SCRIPT_ADDR2 0xff806000
439 #define MV_DTB_ADDR 0xff808000
440 #define MV_INITRD_LENGTH 0x00400000
442 #define CONFIG_SHOW_BOOT_PROGRESS 1
444 #define MV_KERNEL_ADDR_RAM 0x00100000
445 #define MV_DTB_ADDR_RAM 0x00600000
446 #define MV_INITRD_ADDR_RAM 0x01000000
448 #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
449 "then source ${script_addr}; " \
450 "else source ${script_addr2}; " \
452 #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
454 #define CONFIG_EXTRA_ENV_SETTINGS \
456 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
461 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
462 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
463 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
464 "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
465 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
466 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
467 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
468 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
469 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
470 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
471 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
472 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
473 "mv_version=" U_BOOT_VERSION "\0" \
474 "dhcp_client_id=" MV_CI "\0" \
475 "dhcp_vendor-class-identifier=" MV_VCI "\0" \
477 "use_static_ipaddr=no\0" \
478 "static_ipaddr=192.168.90.10\0" \
479 "static_netmask=255.255.255.0\0" \
480 "static_gateway=0.0.0.0\0" \
481 "initrd_name=uInitrd.mvBL-M7-rfs\0" \
485 "tried_bootfromflash=no\0" \
486 "tried_bootfromnet=no\0" \
487 "bootfile=mvblm72625.boot\0" \
490 "mvbcdma_debug=0\0" \
492 "propdev_debug=0\0" \
495 "usb_dr_mode=host\0" \
499 #define CONFIG_FPGA_COUNT 1
500 #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
501 #define CONFIG_FPGA_ALTERA
502 #define CONFIG_FPGA_CYCLON2