sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / MVBLM7.h
1 /*
2  * Copyright (C) Matrix Vision GmbH 2008
3  *
4  * Matrix Vision mvBlueLYNX-M7 configuration file
5  * based on Freescale's MPC8349ITX.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #include <version.h>
15
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_E300     1
20 #define CONFIG_MPC834x  1
21 #define CONFIG_MPC8343  1
22
23 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
24
25 #define CONFIG_SYS_IMMR         0xE0000000
26
27 #define CONFIG_PCI
28 #define CONFIG_PCI_INDIRECT_BRIDGE
29 #define CONFIG_PCI_SKIP_HOST_BRIDGE
30 #define CONFIG_TSEC_ENET
31 #define CONFIG_MPC8XXX_SPI
32 #define CONFIG_HARD_SPI
33 #define MVBLM7_MMC_CS   0x04000000
34 #define CONFIG_MISC_INIT_R
35
36 /* I2C */
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_FSL
39 #define CONFIG_SYS_FSL_I2C_SPEED        100000
40 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
41 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
42 #define CONFIG_SYS_FSL_I2C2_SPEED       100000
43 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
44 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
45
46 /*
47  * DDR Setup
48  */
49 #undef  CONFIG_SPD_EEPROM
50
51 #define CONFIG_SYS_DDR_BASE             0x00000000
52 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
53 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
54 #define CONFIG_SYS_83XX_DDR_USES_CS0    1
55 #define CONFIG_SYS_MEMTEST_START        (60<<20)
56 #define CONFIG_SYS_MEMTEST_END          (70<<20)
57 #define CONFIG_VERY_BIG_RAM
58
59 #define CONFIG_SYS_DDRCDR               (DDRCDR_PZ_HIZ \
60                                         | DDRCDR_NZ_HIZ \
61                                         | DDRCDR_Q_DRN)
62                                         /* 0x22000001 */
63 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
64
65 #define CONFIG_SYS_DDR_SIZE             512
66
67 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
68
69 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
70
71 #define CONFIG_SYS_DDR_TIMING_0         0x00260802
72 #define CONFIG_SYS_DDR_TIMING_1         0x3837c322
73 #define CONFIG_SYS_DDR_TIMING_2         0x0f9848c6
74 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
75
76 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43080008
77 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
78 #define CONFIG_SYS_DDR_INTERVAL         0x02000100
79
80 #define CONFIG_SYS_DDR_MODE             0x04040242
81 #define CONFIG_SYS_DDR_MODE2            0x00800000
82
83 /* Flash */
84 #define CONFIG_SYS_FLASH_CFI
85 #define CONFIG_FLASH_CFI_DRIVER
86 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
87
88 #define CONFIG_SYS_FLASH_BASE           0xFF800000
89 #define CONFIG_SYS_FLASH_SIZE           8
90 #define CONFIG_SYS_FLASH_EMPTY_INFO
91 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
92 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
93 #define CONFIG_SYS_MAX_FLASH_BANKS      1
94 #define CONFIG_SYS_MAX_FLASH_SECT       256
95
96 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
97                                 | BR_PS_16 \
98                                 | BR_MS_GPCM \
99                                 | BR_V)
100 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
101                                 | OR_UPM_XAM \
102                                 | OR_GPCM_CSNT \
103                                 | OR_GPCM_ACS_DIV2 \
104                                 | OR_GPCM_XACS \
105                                 | OR_GPCM_SCY_15 \
106                                 | OR_GPCM_TRLX_SET \
107                                 | OR_GPCM_EHTR_SET \
108                                 | OR_GPCM_EAD)
109 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
110 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
111
112 /*
113  * U-Boot memory configuration
114  */
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
116 #undef  CONFIG_SYS_RAMBOOT
117
118 #define CONFIG_SYS_INIT_RAM_LOCK
119 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000 /* Initial RAM address */
120 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
121
122 #define CONFIG_SYS_GBL_DATA_OFFSET      \
123                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
124 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
125
126 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
127 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
128 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
129
130 /*
131  * Local Bus LCRR and LBCR regs
132  *  LCRR:  DLL bypass, Clock divider is 4
133  * External Local Bus rate is
134  *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
135  */
136 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
137 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
138 #define CONFIG_SYS_LBC_LBCR     0x00000000
139
140 /* LB sdram refresh timer, about 6us */
141 #define CONFIG_SYS_LBC_LSRT     0x32000000
142 /* LB refresh timer prescal, 266MHz/32*/
143 #define CONFIG_SYS_LBC_MRTPR    0x20000000
144
145 /*
146  * Serial Port
147  */
148 #define CONFIG_CONS_INDEX       1
149 #define CONFIG_SYS_NS16550
150 #define CONFIG_SYS_NS16550_SERIAL
151 #define CONFIG_SYS_NS16550_REG_SIZE     1
152 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
153
154 #define CONFIG_SYS_BAUDRATE_TABLE  \
155                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
156
157 #define CONFIG_CONSOLE          ttyS0
158 #define CONFIG_BAUDRATE         115200
159
160 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
161 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
162
163 /* pass open firmware flat tree */
164 #define CONFIG_OF_LIBFDT                1
165 #define CONFIG_OF_BOARD_SETUP           1
166 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
167 #define MV_DTB_NAME     "mvblm7.dtb"
168
169 /*
170  * PCI
171  */
172 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
173 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
174 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000
175 #define CONFIG_SYS_PCI1_MMIO_BASE       \
176                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
177 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
178 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000
179 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
180 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
181 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
182
183 #define CONFIG_NET_RETRY_COUNT  3
184
185 #define CONFIG_PCI_66M
186 #define CONFIG_83XX_CLKIN       66666667
187 #define CONFIG_PCI_PNP
188 #define CONFIG_PCI_SCAN_SHOW
189
190 /* TSEC */
191 #define CONFIG_GMII
192 #define CONFIG_SYS_VSC8601_SKEWFIX
193 #define CONFIG_SYS_VSC8601_SKEW_TX      3
194 #define CONFIG_SYS_VSC8601_SKEW_RX      3
195
196 #define CONFIG_TSEC1
197 #define CONFIG_TSEC2
198
199 #define CONFIG_HAS_ETH0
200 #define CONFIG_TSEC1_NAME       "TSEC0"
201 #define CONFIG_FEC1_PHY_NORXERR
202 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
203 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
204 #define TSEC1_PHY_ADDR          0x10
205 #define TSEC1_PHYIDX            0
206 #define TSEC1_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
207
208 #define CONFIG_HAS_ETH1
209 #define CONFIG_TSEC2_NAME       "TSEC1"
210 #define CONFIG_FEC2_PHY_NORXERR
211 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
212 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
213 #define TSEC2_PHY_ADDR          0x11
214 #define TSEC2_PHYIDX            0
215 #define TSEC2_FLAGS             (TSEC_GIGABIT|TSEC_REDUCED)
216
217 #define CONFIG_ETHPRIME         "TSEC0"
218
219 #define CONFIG_BOOTP_VENDOREX
220 #define CONFIG_BOOTP_SUBNETMASK
221 #define CONFIG_BOOTP_GATEWAY
222 #define CONFIG_BOOTP_DNS
223 #define CONFIG_BOOTP_DNS2
224 #define CONFIG_BOOTP_HOSTNAME
225 #define CONFIG_BOOTP_BOOTFILESIZE
226 #define CONFIG_BOOTP_BOOTPATH
227 #define CONFIG_BOOTP_NTPSERVER
228 #define CONFIG_BOOTP_RANDOM_DELAY
229 #define CONFIG_BOOTP_SEND_HOSTNAME
230 #define CONFIG_LIB_RAND
231
232 /* USB */
233 #define CONFIG_SYS_USB_HOST
234 #define CONFIG_USB_EHCI
235 #define CONFIG_USB_EHCI_FSL
236 #define CONFIG_HAS_FSL_DR_USB
237 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
238
239 /*
240  * Environment
241  */
242 #undef  CONFIG_SYS_FLASH_PROTECTION
243 #define CONFIG_ENV_OVERWRITE
244
245 #define CONFIG_ENV_IS_IN_FLASH  1
246 #define CONFIG_ENV_ADDR         0xFF800000
247 #define CONFIG_ENV_SIZE         0x2000
248 #define CONFIG_ENV_SECT_SIZE    0x2000
249 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
250 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
251
252 #define CONFIG_LOADS_ECHO
253 #define CONFIG_SYS_LOADS_BAUD_CHANGE
254
255 /*
256  * Command line configuration.
257  */
258 #include <config_cmd_default.h>
259
260 #define CONFIG_CMD_CACHE
261 #define CONFIG_CMD_IRQ
262 #define CONFIG_CMD_NET
263 #define CONFIG_CMD_MII
264 #define CONFIG_CMD_PING
265 #define CONFIG_CMD_DHCP
266 #define CONFIG_CMD_SDRAM
267 #define CONFIG_CMD_PCI
268 #define CONFIG_CMD_I2C
269 #define CONFIG_CMD_FPGA
270 #define CONFIG_CMD_FPGA_LOADMK
271 #define CONFIG_CMD_USB
272 #define CONFIG_DOS_PARTITION
273
274 #undef CONFIG_WATCHDOG
275
276 /*
277  * Miscellaneous configurable options
278  */
279 #define CONFIG_SYS_LONGHELP
280 #define CONFIG_CMDLINE_EDITING
281 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
282 #define CONFIG_SYS_HUSH_PARSER
283
284 /* default load address */
285 #define CONFIG_SYS_LOAD_ADDR    0x2000000
286 /* default location for tftp and bootm */
287 #define CONFIG_LOADADDR 0x200000
288
289 #define CONFIG_SYS_PROMPT       "mvBL-M7> "
290 #define CONFIG_SYS_CBSIZE       256
291
292 #define CONFIG_SYS_PBSIZE       \
293                         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
294 #define CONFIG_SYS_MAXARGS      16
295 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
296
297 /*
298  * For booting Linux, the board info and command line data
299  * have to be in the first 256 MB of memory, since this is
300  * the maximum mapped by the Linux kernel during initialization.
301  */
302                                 /* Initial Memory map for Linux*/
303 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
304
305 #define CONFIG_SYS_HRCW_LOW     0x0
306 #define CONFIG_SYS_HRCW_HIGH    0x0
307
308 /*
309  * System performance
310  */
311 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
312 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
313 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
314 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
315
316 /* clocking */
317 #define CONFIG_SYS_SCCR_ENCCM           0
318 #define CONFIG_SYS_SCCR_USBMPHCM        0
319 #define CONFIG_SYS_SCCR_USBDRCM 2
320 #define CONFIG_SYS_SCCR_TSEC1CM 1
321 #define CONFIG_SYS_SCCR_TSEC2CM 1
322
323 #define CONFIG_SYS_SICRH        0x1fef0003
324 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
325
326 #define CONFIG_SYS_HID0_INIT    0x000000000
327 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
328                                  HID0_ENABLE_INSTRUCTION_CACHE)
329
330 #define CONFIG_SYS_HID2 HID2_HBE
331 #define CONFIG_HIGH_BATS        1
332
333 /* DDR  */
334 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
335                                 | BATL_PP_RW \
336                                 | BATL_MEMCOHERENCE)
337 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
338                                 | BATU_BL_256M \
339                                 | BATU_VS \
340                                 | BATU_VP)
341
342 /* PCI  */
343 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
344                                 | BATL_PP_RW \
345                                 | BATL_MEMCOHERENCE)
346 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
347                                 | BATU_BL_256M \
348                                 | BATU_VS \
349                                 | BATU_VP)
350 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
351                                 | BATL_PP_RW \
352                                 | BATL_CACHEINHIBIT \
353                                 | BATL_GUARDEDSTORAGE)
354 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
355                                 | BATU_BL_256M \
356                                 | BATU_VS \
357                                 | BATU_VP)
358
359 /* no PCI2 */
360 #define CONFIG_SYS_IBAT3L       0
361 #define CONFIG_SYS_IBAT3U       0
362 #define CONFIG_SYS_IBAT4L       0
363 #define CONFIG_SYS_IBAT4U       0
364
365 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
366 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
367                                 | BATL_PP_RW \
368                                 | BATL_CACHEINHIBIT \
369                                 | BATL_GUARDEDSTORAGE)
370 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
371                                 | BATU_BL_256M \
372                                 | BATU_VS \
373                                 | BATU_VP)
374
375 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
376 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
377                                 | BATL_PP_RW \
378                                 | BATL_MEMCOHERENCE \
379                                 | BATL_GUARDEDSTORAGE)
380 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
381                                 | BATU_BL_256M \
382                                 | BATU_VS \
383                                 | BATU_VP)
384 #define CONFIG_SYS_IBAT7L       0
385 #define CONFIG_SYS_IBAT7U       0
386
387 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
388 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
389 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
390 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
391 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
392 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
393 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
394 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
395 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
396 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
397 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
398 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
399 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
400 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
401 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
402 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
403
404 /*
405  * Environment Configuration
406  */
407 #define CONFIG_ENV_OVERWRITE
408
409 #define CONFIG_NETDEV           eth0
410
411 /* Default path and filenames */
412 #define CONFIG_BOOTDELAY                5
413 #define CONFIG_AUTOBOOT_KEYED
414 #define CONFIG_AUTOBOOT_STOP_STR        "s"
415 #define CONFIG_ZERO_BOOTDELAY_CHECK
416 #define CONFIG_RESET_TO_RETRY           1000
417
418 #define MV_CI                   "mvBL-M7"
419 #define MV_VCI                  "mvBL-M7"
420 #define MV_FPGA_DATA            0xfff40000
421 #define MV_FPGA_SIZE            0
422 #define MV_KERNEL_ADDR          0xff810000
423 #define MV_INITRD_ADDR          0xffb00000
424 #define MV_SCRIPT_ADDR          0xff804000
425 #define MV_SCRIPT_ADDR2         0xff806000
426 #define MV_DTB_ADDR             0xff808000
427 #define MV_INITRD_LENGTH        0x00400000
428
429 #define CONFIG_SHOW_BOOT_PROGRESS 1
430
431 #define MV_KERNEL_ADDR_RAM      0x00100000
432 #define MV_DTB_ADDR_RAM         0x00600000
433 #define MV_INITRD_ADDR_RAM      0x01000000
434
435 #define CONFIG_BOOTCOMMAND      "if imi ${script_addr}; "               \
436                                         "then source ${script_addr}; "  \
437                                         "else source ${script_addr2}; " \
438                                 "fi;"
439 #define CONFIG_BOOTARGS         "root=/dev/ram ro rootfstype=squashfs"
440
441 #define CONFIG_EXTRA_ENV_SETTINGS                               \
442         "console_nr=0\0"                                        \
443         "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"           \
444         "stdin=serial\0"                                        \
445         "stdout=serial\0"                                       \
446         "stderr=serial\0"                                       \
447         "fpga=0\0"                                              \
448         "fpgadata=" __stringify(MV_FPGA_DATA) "\0"                      \
449         "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"          \
450         "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"         \
451         "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"               \
452         "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"              \
453         "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"      \
454         "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"              \
455         "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"      \
456         "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"  \
457         "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"                    \
458         "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"            \
459         "dtb_name=" __stringify(MV_DTB_NAME) "\0"                       \
460         "mv_version=" U_BOOT_VERSION "\0"                       \
461         "dhcp_client_id=" MV_CI "\0"                            \
462         "dhcp_vendor-class-identifier=" MV_VCI "\0"             \
463         "netretry=no\0"                                         \
464         "use_static_ipaddr=no\0"                                \
465         "static_ipaddr=192.168.90.10\0"                         \
466         "static_netmask=255.255.255.0\0"                        \
467         "static_gateway=0.0.0.0\0"                              \
468         "initrd_name=uInitrd.mvBL-M7-rfs\0"                     \
469         "zcip=no\0"                                             \
470         "netboot=yes\0"                                         \
471         "mvtest=Ff\0"                                           \
472         "tried_bootfromflash=no\0"                              \
473         "tried_bootfromnet=no\0"                                \
474         "bootfile=mvblm72625.boot\0"                            \
475         "use_dhcp=yes\0"                                        \
476         "gev_start=yes\0"                                       \
477         "mvbcdma_debug=0\0"                                     \
478         "mvbcia_debug=0\0"                                      \
479         "propdev_debug=0\0"                                     \
480         "gevss_debug=0\0"                                       \
481         "watchdog=0\0"                                          \
482         "usb_dr_mode=host\0"                                    \
483         "sensor_cnt=2\0"                                        \
484         ""
485
486 #define CONFIG_FPGA_COUNT       1
487 #define CONFIG_FPGA
488 #define CONFIG_FPGA_ALTERA
489 #define CONFIG_FPGA_CYCLON2
490
491 #endif