3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the MUSENKI board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_MPC824X 1
45 #define CONFIG_MPC8245 1
46 #define CONFIG_MUSENKI 1
48 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
50 #define CONFIG_CONS_INDEX 1
51 #define CONFIG_BAUDRATE 9600
53 #define CONFIG_BOOTDELAY 5
59 #define CONFIG_BOOTP_BOOTFILESIZE
60 #define CONFIG_BOOTP_BOOTPATH
61 #define CONFIG_BOOTP_GATEWAY
62 #define CONFIG_BOOTP_HOSTNAME
66 * Command line configuration.
68 #include <config_cmd_default.h>
72 * Miscellaneous configurable options
74 #undef CONFIG_SYS_LONGHELP /* undef to save memory */
75 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
76 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
80 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
81 #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
82 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
83 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
85 /*-----------------------------------------------------------------------
87 *-----------------------------------------------------------------------
89 #define CONFIG_PCI /* include pci support */
95 #define PCI_ENET0_IOADDR 0x80000000
96 #define PCI_ENET0_MEMADDR 0x80000000
97 #define PCI_ENET1_IOADDR 0x81000000
98 #define PCI_ENET1_MEMADDR 0x81000000
101 /*-----------------------------------------------------------------------
102 * Start addresses for the final memory configuration
103 * (Set up by the startup code)
104 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
106 #define CONFIG_SYS_SDRAM_BASE 0x00000000
108 #define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
109 #define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
110 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
112 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
113 * reset vector is actually located at FFB00100, but the 8245
116 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
118 #define CONFIG_SYS_EUMB_ADDR 0xFC000000
120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
121 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
122 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
124 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
125 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
127 /* Maximum amount of RAM.
129 #define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */
132 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
133 #undef CONFIG_SYS_RAMBOOT
135 #define CONFIG_SYS_RAMBOOT
139 * NS16550 Configuration
141 #define CONFIG_SYS_NS16550
142 #define CONFIG_SYS_NS16550_SERIAL
144 #define CONFIG_SYS_NS16550_REG_SIZE 1
146 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
148 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
149 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
151 /*-----------------------------------------------------------------------
152 * Definitions for initial stack pointer and data area
155 /* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
156 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
157 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 * For the detail description refer to the MPC8240 user's manual.
168 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
169 #define CONFIG_SYS_HZ 1000
171 /* Bit-field values for MCCR1.
173 #define CONFIG_SYS_ROMNAL 7
174 #define CONFIG_SYS_ROMFAL 11
175 #define CONFIG_SYS_DBUS_SIZE 0x3
177 /* Bit-field values for MCCR2.
179 #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
180 #define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
182 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
184 #define CONFIG_SYS_BSTOPRE 121
186 /* Bit-field values for MCCR3.
188 #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
190 /* Bit-field values for MCCR4.
192 #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
193 #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
194 #define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
195 #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
196 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
197 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
198 #define CONFIG_SYS_EXTROM 1
199 #define CONFIG_SYS_REGDIMM 0
201 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
203 #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
205 /* Memory bank settings.
206 * Only bits 20-29 are actually used from these vales to set the
207 * start/end addresses. The upper two bits will always be 0, and the lower
208 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
209 * address. Refer to the MPC8240 book.
212 #define CONFIG_SYS_BANK0_START 0x00000000
213 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
214 #define CONFIG_SYS_BANK0_ENABLE 1
215 #define CONFIG_SYS_BANK1_START 0x3ff00000
216 #define CONFIG_SYS_BANK1_END 0x3fffffff
217 #define CONFIG_SYS_BANK1_ENABLE 0
218 #define CONFIG_SYS_BANK2_START 0x3ff00000
219 #define CONFIG_SYS_BANK2_END 0x3fffffff
220 #define CONFIG_SYS_BANK2_ENABLE 0
221 #define CONFIG_SYS_BANK3_START 0x3ff00000
222 #define CONFIG_SYS_BANK3_END 0x3fffffff
223 #define CONFIG_SYS_BANK3_ENABLE 0
224 #define CONFIG_SYS_BANK4_START 0x3ff00000
225 #define CONFIG_SYS_BANK4_END 0x3fffffff
226 #define CONFIG_SYS_BANK4_ENABLE 0
227 #define CONFIG_SYS_BANK5_START 0x3ff00000
228 #define CONFIG_SYS_BANK5_END 0x3fffffff
229 #define CONFIG_SYS_BANK5_ENABLE 0
230 #define CONFIG_SYS_BANK6_START 0x3ff00000
231 #define CONFIG_SYS_BANK6_END 0x3fffffff
232 #define CONFIG_SYS_BANK6_ENABLE 0
233 #define CONFIG_SYS_BANK7_START 0x3ff00000
234 #define CONFIG_SYS_BANK7_END 0x3fffffff
235 #define CONFIG_SYS_BANK7_ENABLE 0
237 #define CONFIG_SYS_ODCR 0xff
239 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
240 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
242 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
243 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
245 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
246 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
248 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
249 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
251 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
252 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
253 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
254 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
255 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
256 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
257 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
258 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
261 * For booting Linux, the board info and command line data
262 * have to be in the first 8 MB of memory, since this is
263 * the maximum mapped by the Linux kernel during initialization.
265 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
267 /*-----------------------------------------------------------------------
270 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
271 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
273 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
274 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
277 /* Warining: environment is not EMBEDDED in the U-Boot code.
278 * It's stored in flash separately.
280 #define CONFIG_ENV_IS_IN_FLASH 1
281 #define CONFIG_ENV_ADDR 0xFFFF0000
282 #define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */
283 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */
285 /*-----------------------------------------------------------------------
286 * Cache Configuration
288 #define CONFIG_SYS_CACHELINE_SIZE 32
289 #if defined(CONFIG_CMD_KGDB)
290 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
293 #endif /* __CONFIG_H */