2 * Copyright 2006 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MPC8641HPCN board configuration file
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx 1 /* MPC86xx */
37 #define CONFIG_MPC8641 1 /* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
43 #define CONFIG_SYS_DIAG_ADDR 0xff800000
46 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
49 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
50 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
55 #define CONFIG_TSEC_ENET /* tsec ethernet support */
56 #define CONFIG_ENV_OVERWRITE
58 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
60 #define CONFIG_ALTIVEC 1
63 * L2CR setup -- make sure this is right for your board!
67 #define L2_ENABLE (L2CR_L2E)
69 #ifndef CONFIG_SYS_CLK_FREQ
71 extern unsigned long get_board_sys_clk(unsigned long dummy);
73 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
79 #define CONFIG_SYS_MEMTEST_END 0x00400000
82 * Base addresses -- Note these are effective addresses where the
83 * actual resources get mapped (not physical addresses)
85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
89 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
90 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
95 #define CONFIG_FSL_DDR2
96 #undef CONFIG_FSL_DDR_INTERACTIVE
97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
98 #define CONFIG_DDR_SPD
100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
105 #define CONFIG_VERY_BIG_RAM
107 #define MPC86xx_DDR_SDRAM_CLK_CNTL
109 #define CONFIG_NUM_DDR_CONTROLLERS 2
110 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
111 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
114 * I2C addresses of SPD EEPROMs
116 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
117 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
118 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
119 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
123 * These are used when DDR doesn't use SPD.
125 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
126 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
127 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
129 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
130 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
131 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
132 #define CONFIG_SYS_DDR_MODE_1 0x00480432
133 #define CONFIG_SYS_DDR_MODE_2 0x00000000
134 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
135 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
137 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
138 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
139 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
140 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
143 * FIXME: Not used in fixed_sdram function
145 #define CONFIG_SYS_DDR_MODE 0x00000022
146 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
147 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
148 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
149 #define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
150 #define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
153 #define CONFIG_ID_EEPROM
154 #define CONFIG_SYS_I2C_EEPROM_NXID
155 #define CONFIG_ID_EEPROM
156 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
160 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
161 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
162 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
163 * However, when u-boot comes up, the flash_init needs hard start addresses
164 * to build its info table. For user convenience, the flash addresses is
165 * fe800000 and ff800000. That way, u-boot knows where the flash is
166 * and the user can download u-boot code from promjet to fef00000, a
167 * more intuitive location than fe700000.
169 * Note that, on switching the boot location, fef00000 becomes fff00000.
171 #define CONFIG_SYS_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
172 #define CONFIG_SYS_FLASH_BASE2 0xff800000
174 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
176 #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
177 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
179 #define CONFIG_SYS_BR1_PRELIM 0xfe001001 /* port size 16bit */
180 #define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
182 #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
183 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
185 #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
186 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
189 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
190 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
191 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
192 #define PIXIS_VER 0x1 /* Board version at offset 1 */
193 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
194 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
195 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
196 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
197 #define PIXIS_VCTL 0x10 /* VELA Control Register */
198 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
199 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
200 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
201 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
202 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
203 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
204 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
205 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
207 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
208 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
210 #undef CONFIG_SYS_FLASH_CHECKSUM
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
213 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
215 #define CONFIG_FLASH_CFI_DRIVER
216 #define CONFIG_SYS_FLASH_CFI
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
220 #define CONFIG_SYS_RAMBOOT
222 #undef CONFIG_SYS_RAMBOOT
225 #if defined(CONFIG_SYS_RAMBOOT)
226 #undef CONFIG_SPD_EEPROM
227 #define CONFIG_SYS_SDRAM_SIZE 256
230 #undef CONFIG_CLOCKS_IN_MHZ
232 #define CONFIG_L1_INIT_RAM
233 #define CONFIG_SYS_INIT_RAM_LOCK 1
234 #ifndef CONFIG_SYS_INIT_RAM_LOCK
235 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
237 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
239 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
241 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
245 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
246 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
249 #define CONFIG_CONS_INDEX 1
250 #undef CONFIG_SERIAL_SOFTWARE_FIFO
251 #define CONFIG_SYS_NS16550
252 #define CONFIG_SYS_NS16550_SERIAL
253 #define CONFIG_SYS_NS16550_REG_SIZE 1
254 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
256 #define CONFIG_SYS_BAUDRATE_TABLE \
257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
262 /* Use the HUSH parser */
263 #define CONFIG_SYS_HUSH_PARSER
264 #ifdef CONFIG_SYS_HUSH_PARSER
265 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
269 * Pass open firmware flat tree to kernel
271 #define CONFIG_OF_LIBFDT 1
272 #define CONFIG_OF_BOARD_SETUP 1
273 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
276 #define CONFIG_SYS_64BIT_VSPRINTF 1
277 #define CONFIG_SYS_64BIT_STRTOUL 1
282 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
283 #define CONFIG_HARD_I2C /* I2C with hardware support*/
284 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
285 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
286 #define CONFIG_SYS_I2C_SLAVE 0x7F
287 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
288 #define CONFIG_SYS_I2C_OFFSET 0x3100
293 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
294 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
295 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
299 * Addresses are mapped 1-1.
301 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
302 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
303 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
304 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
305 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
306 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
308 /* PCI view of System Memory */
309 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
310 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
311 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
314 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
315 #define _IO_BASE 0x00000000
317 #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
318 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
319 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
320 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
321 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
322 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
324 #if defined(CONFIG_PCI)
326 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
328 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
330 #define CONFIG_NET_MULTI
331 #define CONFIG_PCI_PNP /* do pci plug-and-play */
333 #define CONFIG_RTL8139
335 #undef CONFIG_EEPRO100
338 /************************************************************
340 ************************************************************/
341 #define CONFIG_PCI_OHCI 1
342 #define CONFIG_USB_OHCI_NEW 1
343 #define CONFIG_USB_KEYBOARD 1
344 #define CONFIG_SYS_DEVICE_DEREGISTER
345 #define CONFIG_SYS_USB_EVENT_POLL 1
346 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
347 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
348 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
350 #if !defined(CONFIG_PCI_PNP)
351 #define PCI_ENET0_IOADDR 0xe0000000
352 #define PCI_ENET0_MEMADDR 0xe0000000
353 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
356 /*PCIE video card used*/
357 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
359 /*PCI video card used*/
360 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
365 #if defined(CONFIG_VIDEO)
366 #define CONFIG_BIOSEMU
367 #define CONFIG_CFB_CONSOLE
368 #define CONFIG_VIDEO_SW_CURSOR
369 #define CONFIG_VGA_AS_SINGLE_DEVICE
370 #define CONFIG_ATI_RADEON_FB
371 #define CONFIG_VIDEO_LOGO
372 /*#define CONFIG_CONSOLE_CURSOR*/
373 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
376 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
378 #define CONFIG_DOS_PARTITION
379 #define CONFIG_SCSI_AHCI
381 #ifdef CONFIG_SCSI_AHCI
382 #define CONFIG_SATA_ULI5288
383 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
384 #define CONFIG_SYS_SCSI_MAX_LUN 1
385 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
386 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
389 #define CONFIG_MPC86XX_PCI2
391 #endif /* CONFIG_PCI */
393 #if defined(CONFIG_TSEC_ENET)
395 #ifndef CONFIG_NET_MULTI
396 #define CONFIG_NET_MULTI 1
399 #define CONFIG_MII 1 /* MII PHY management */
401 #define CONFIG_TSEC1 1
402 #define CONFIG_TSEC1_NAME "eTSEC1"
403 #define CONFIG_TSEC2 1
404 #define CONFIG_TSEC2_NAME "eTSEC2"
405 #define CONFIG_TSEC3 1
406 #define CONFIG_TSEC3_NAME "eTSEC3"
407 #define CONFIG_TSEC4 1
408 #define CONFIG_TSEC4_NAME "eTSEC4"
410 #define TSEC1_PHY_ADDR 0
411 #define TSEC2_PHY_ADDR 1
412 #define TSEC3_PHY_ADDR 2
413 #define TSEC4_PHY_ADDR 3
414 #define TSEC1_PHYIDX 0
415 #define TSEC2_PHYIDX 0
416 #define TSEC3_PHYIDX 0
417 #define TSEC4_PHYIDX 0
418 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
419 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
421 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423 #define CONFIG_ETHPRIME "eTSEC1"
425 #endif /* CONFIG_TSEC_ENET */
428 * BAT0 2G Cacheable, non-guarded
431 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
432 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
433 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
434 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
437 * BAT1 1G Cache-inhibited, guarded
438 * 0x8000_0000 512M PCI-Express 1 Memory
439 * 0xa000_0000 512M PCI-Express 2 Memory
440 * Changed it for operating from 0xd0000000
442 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
443 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
444 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
445 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
446 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
449 * BAT2 512M Cache-inhibited, guarded
450 * 0xc000_0000 512M RapidIO Memory
452 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
453 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
454 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
455 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
456 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
459 * BAT3 4M Cache-inhibited, guarded
460 * 0xf800_0000 4M CCSR
462 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
463 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
464 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
465 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
466 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
469 * BAT4 32M Cache-inhibited, guarded
470 * 0xe200_0000 16M PCI-Express 1 I/O
471 * 0xe300_0000 16M PCI-Express 2 I/0
472 * Note that this is at 0xe0000000
474 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
475 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
476 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
477 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
478 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
481 * BAT5 128K Cacheable, non-guarded
482 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
484 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
485 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
486 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
487 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
490 * BAT6 32M Cache-inhibited, guarded
491 * 0xfe00_0000 32M FLASH
493 #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
494 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
495 #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
496 #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
497 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
499 #define CONFIG_SYS_DBAT7L 0x00000000
500 #define CONFIG_SYS_DBAT7U 0x00000000
501 #define CONFIG_SYS_IBAT7L 0x00000000
502 #define CONFIG_SYS_IBAT7U 0x00000000
507 #ifndef CONFIG_SYS_RAMBOOT
508 #define CONFIG_ENV_IS_IN_FLASH 1
509 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
510 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
511 #define CONFIG_ENV_SIZE 0x2000
513 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
514 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
515 #define CONFIG_ENV_SIZE 0x2000
518 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
519 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
525 #define CONFIG_BOOTP_BOOTFILESIZE
526 #define CONFIG_BOOTP_BOOTPATH
527 #define CONFIG_BOOTP_GATEWAY
528 #define CONFIG_BOOTP_HOSTNAME
532 * Command line configuration.
534 #include <config_cmd_default.h>
536 #define CONFIG_CMD_PING
537 #define CONFIG_CMD_I2C
538 #define CONFIG_CMD_REGINFO
540 #if defined(CONFIG_SYS_RAMBOOT)
541 #undef CONFIG_CMD_ENV
544 #if defined(CONFIG_PCI)
545 #define CONFIG_CMD_PCI
546 #define CONFIG_CMD_SCSI
547 #define CONFIG_CMD_EXT2
548 #define CONFIG_CMD_USB
552 #undef CONFIG_WATCHDOG /* watchdog disabled */
555 * Miscellaneous configurable options
557 #define CONFIG_SYS_LONGHELP /* undef to save memory */
558 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
559 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
560 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
562 #if defined(CONFIG_CMD_KGDB)
563 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
565 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
568 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
569 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
571 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
574 * For booting Linux, the board info and command line data
575 * have to be in the first 8 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
578 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
581 * Internal Definitions
585 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
586 #define BOOTFLAG_WARM 0x02 /* Software reboot */
588 #if defined(CONFIG_CMD_KGDB)
589 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
590 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
594 * Environment Configuration
597 /* The mac addresses for all ethernet interface */
598 #if defined(CONFIG_TSEC_ENET)
599 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
600 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
601 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
602 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
605 #define CONFIG_HAS_ETH0 1
606 #define CONFIG_HAS_ETH1 1
607 #define CONFIG_HAS_ETH2 1
608 #define CONFIG_HAS_ETH3 1
610 #define CONFIG_IPADDR 192.168.1.100
612 #define CONFIG_HOSTNAME unknown
613 #define CONFIG_ROOTPATH /opt/nfsroot
614 #define CONFIG_BOOTFILE uImage
615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
617 #define CONFIG_SERVERIP 192.168.1.1
618 #define CONFIG_GATEWAYIP 192.168.1.1
619 #define CONFIG_NETMASK 255.255.255.0
621 /* default location for tftp and bootm */
622 #define CONFIG_LOADADDR 1000000
624 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
625 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
627 #define CONFIG_BAUDRATE 115200
629 #define CONFIG_EXTRA_ENV_SETTINGS \
631 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
632 "tftpflash=tftpboot $loadaddr $uboot; " \
633 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
634 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
635 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
636 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
637 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
638 "consoledev=ttyS0\0" \
639 "ramdiskaddr=2000000\0" \
640 "ramdiskfile=your.ramdisk.u-boot\0" \
642 "fdtfile=mpc8641_hpcn.dtb\0" \
643 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
644 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
648 #define CONFIG_NFSBOOTCOMMAND \
649 "setenv bootargs root=/dev/nfs rw " \
650 "nfsroot=$serverip:$rootpath " \
651 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
652 "console=$consoledev,$baudrate $othbootargs;" \
653 "tftp $loadaddr $bootfile;" \
654 "tftp $fdtaddr $fdtfile;" \
655 "bootm $loadaddr - $fdtaddr"
657 #define CONFIG_RAMBOOTCOMMAND \
658 "setenv bootargs root=/dev/ram rw " \
659 "console=$consoledev,$baudrate $othbootargs;" \
660 "tftp $ramdiskaddr $ramdiskfile;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr $ramdiskaddr $fdtaddr"
665 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
667 #endif /* __CONFIG_H */