2 * Copyright 2006 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MPC8641HPCN board configuration file
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx 1 /* MPC86xx */
37 #define CONFIG_MPC8641 1 /* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
43 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
46 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
49 * virtual address to be used for temporary mappings. There
50 * should be 128k free at this VA.
52 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
55 * set this to enable Rapid IO. PCI and RIO are mutually exclusive
57 /*#define CONFIG_RIO 1*/
59 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
60 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
61 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
62 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
63 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
66 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
68 #define CONFIG_TSEC_ENET /* tsec ethernet support */
69 #define CONFIG_ENV_OVERWRITE
71 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
73 #define CONFIG_ALTIVEC 1
76 * L2CR setup -- make sure this is right for your board!
80 #define L2_ENABLE (L2CR_L2E)
82 #ifndef CONFIG_SYS_CLK_FREQ
84 extern unsigned long get_board_sys_clk(unsigned long dummy);
86 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
89 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
91 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
92 #define CONFIG_SYS_MEMTEST_END 0x00400000
95 * Base addresses -- Note these are effective addresses where the
96 * actual resources get mapped (not physical addresses)
98 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
99 #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
100 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
102 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
103 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
108 #define CONFIG_FSL_DDR2
109 #undef CONFIG_FSL_DDR_INTERACTIVE
110 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
111 #define CONFIG_DDR_SPD
113 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
118 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
119 #define CONFIG_VERY_BIG_RAM
121 #define MPC86xx_DDR_SDRAM_CLK_CNTL
123 #define CONFIG_NUM_DDR_CONTROLLERS 2
124 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
125 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
128 * I2C addresses of SPD EEPROMs
130 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
131 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
132 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
133 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
137 * These are used when DDR doesn't use SPD.
139 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
141 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
143 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
144 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
145 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
146 #define CONFIG_SYS_DDR_MODE_1 0x00480432
147 #define CONFIG_SYS_DDR_MODE_2 0x00000000
148 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
151 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
152 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
153 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
154 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
156 #define CONFIG_ID_EEPROM
157 #define CONFIG_SYS_I2C_EEPROM_NXID
158 #define CONFIG_ID_EEPROM
159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
162 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
166 /* Convert an address into the right format for the BR registers */
167 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
169 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) \
170 | 0x00001001) /* port size 16bit */
171 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
173 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE) \
174 | 0x00001001) /* port size 16bit */
175 #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
177 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE) \
178 | 0x00000801) /* port size 8bit */
179 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
182 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
183 #define PIXIS_BASE (CONFIG_SYS_CCSRBAR + 0x00100000) /* PIXIS registers */
184 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
185 #define PIXIS_VER 0x1 /* Board version at offset 1 */
186 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
187 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
188 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
189 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
190 #define PIXIS_VCTL 0x10 /* VELA Control Register */
191 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
192 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
193 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
194 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
195 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
196 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
197 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
198 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
200 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
201 #define CF_BASE (PIXIS_BASE + 0x00100000)
203 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
206 #undef CONFIG_SYS_FLASH_CHECKSUM
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
209 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
211 #define CONFIG_FLASH_CFI_DRIVER
212 #define CONFIG_SYS_FLASH_CFI
213 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
216 #define CONFIG_SYS_RAMBOOT
218 #undef CONFIG_SYS_RAMBOOT
221 #if defined(CONFIG_SYS_RAMBOOT)
222 #undef CONFIG_SPD_EEPROM
223 #define CONFIG_SYS_SDRAM_SIZE 256
226 #undef CONFIG_CLOCKS_IN_MHZ
228 #define CONFIG_L1_INIT_RAM
229 #define CONFIG_SYS_INIT_RAM_LOCK 1
230 #ifndef CONFIG_SYS_INIT_RAM_LOCK
231 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
233 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
235 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
237 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
239 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
241 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
242 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
245 #define CONFIG_CONS_INDEX 1
246 #undef CONFIG_SERIAL_SOFTWARE_FIFO
247 #define CONFIG_SYS_NS16550
248 #define CONFIG_SYS_NS16550_SERIAL
249 #define CONFIG_SYS_NS16550_REG_SIZE 1
250 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
252 #define CONFIG_SYS_BAUDRATE_TABLE \
253 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
255 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
256 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
258 /* Use the HUSH parser */
259 #define CONFIG_SYS_HUSH_PARSER
260 #ifdef CONFIG_SYS_HUSH_PARSER
261 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
265 * Pass open firmware flat tree to kernel
267 #define CONFIG_OF_LIBFDT 1
268 #define CONFIG_OF_BOARD_SETUP 1
269 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
272 #define CONFIG_SYS_64BIT_VSPRINTF 1
273 #define CONFIG_SYS_64BIT_STRTOUL 1
278 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
279 #define CONFIG_HARD_I2C /* I2C with hardware support*/
280 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
281 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
282 #define CONFIG_SYS_I2C_SLAVE 0x7F
283 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
284 #define CONFIG_SYS_I2C_OFFSET 0x3100
289 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
290 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
291 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
295 * Addresses are mapped 1-1.
297 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
298 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
299 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
301 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
302 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
305 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
306 #define _IO_BASE 0x00000000
308 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
309 + CONFIG_SYS_PCI1_MEM_SIZE)
310 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
311 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
312 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
313 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
314 + CONFIG_SYS_PCI1_IO_SIZE)
315 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
317 #if defined(CONFIG_PCI)
319 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
321 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
323 #define CONFIG_NET_MULTI
324 #define CONFIG_PCI_PNP /* do pci plug-and-play */
326 #define CONFIG_RTL8139
328 #undef CONFIG_EEPRO100
331 /************************************************************
333 ************************************************************/
334 #define CONFIG_PCI_OHCI 1
335 #define CONFIG_USB_OHCI_NEW 1
336 #define CONFIG_USB_KEYBOARD 1
337 #define CONFIG_SYS_DEVICE_DEREGISTER
338 #define CONFIG_SYS_USB_EVENT_POLL 1
339 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
340 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
341 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
343 /*PCIE video card used*/
344 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS
346 /*PCI video card used*/
347 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
352 #if defined(CONFIG_VIDEO)
353 #define CONFIG_BIOSEMU
354 #define CONFIG_CFB_CONSOLE
355 #define CONFIG_VIDEO_SW_CURSOR
356 #define CONFIG_VGA_AS_SINGLE_DEVICE
357 #define CONFIG_ATI_RADEON_FB
358 #define CONFIG_VIDEO_LOGO
359 /*#define CONFIG_CONSOLE_CURSOR*/
360 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS
363 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
365 #define CONFIG_DOS_PARTITION
366 #define CONFIG_SCSI_AHCI
368 #ifdef CONFIG_SCSI_AHCI
369 #define CONFIG_SATA_ULI5288
370 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
371 #define CONFIG_SYS_SCSI_MAX_LUN 1
372 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
373 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
376 #define CONFIG_MPC86XX_PCI2
378 #endif /* CONFIG_PCI */
380 #if defined(CONFIG_TSEC_ENET)
382 #ifndef CONFIG_NET_MULTI
383 #define CONFIG_NET_MULTI 1
386 #define CONFIG_MII 1 /* MII PHY management */
388 #define CONFIG_TSEC1 1
389 #define CONFIG_TSEC1_NAME "eTSEC1"
390 #define CONFIG_TSEC2 1
391 #define CONFIG_TSEC2_NAME "eTSEC2"
392 #define CONFIG_TSEC3 1
393 #define CONFIG_TSEC3_NAME "eTSEC3"
394 #define CONFIG_TSEC4 1
395 #define CONFIG_TSEC4_NAME "eTSEC4"
397 #define TSEC1_PHY_ADDR 0
398 #define TSEC2_PHY_ADDR 1
399 #define TSEC3_PHY_ADDR 2
400 #define TSEC4_PHY_ADDR 3
401 #define TSEC1_PHYIDX 0
402 #define TSEC2_PHYIDX 0
403 #define TSEC3_PHYIDX 0
404 #define TSEC4_PHYIDX 0
405 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
406 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
407 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
408 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
410 #define CONFIG_ETHPRIME "eTSEC1"
412 #endif /* CONFIG_TSEC_ENET */
415 * BAT0 2G Cacheable, non-guarded
418 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
419 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
420 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
421 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
426 #define CONFIG_SYS_DBAT1L 0
427 #define CONFIG_SYS_DBAT1U 0
428 #define CONFIG_SYS_IBAT1L 0
429 #define CONFIG_SYS_IBAT1U 0
432 * BAT2 1G Cache-inhibited, guarded
433 * 0x8000_0000 512M PCI-Express 1 Memory
434 * 0xa000_0000 512M PCI-Express 2 Memory
435 * Changed it for operating from 0xd0000000
438 * BAT2 512M Cache-inhibited, guarded
439 * 0xc000_0000 512M RapidIO Memory
442 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
443 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
444 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \
446 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
448 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
449 #else /* CONFIG_RIO */
450 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
451 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
452 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
453 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
454 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
458 * BAT3 4M Cache-inhibited, guarded
459 * 0xf800_0000 4M CCSR
461 #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
462 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
463 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
464 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
465 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
468 * BAT4 32M Cache-inhibited, guarded
469 * 0xe200_0000 16M PCI-Express 1 I/O
470 * 0xe300_0000 16M PCI-Express 2 I/0
471 * Note that this is at 0xe0000000
473 #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
474 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
475 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
476 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
477 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
480 * BAT5 128K Cacheable, non-guarded
481 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
483 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
484 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
485 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
486 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
489 * BAT6 8M Cache-inhibited, guarded
490 * 0xff80_0000 8M FLASH
492 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
493 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
494 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
496 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW \
498 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
500 #define CONFIG_SYS_DBAT7L 0x00000000
501 #define CONFIG_SYS_DBAT7U 0x00000000
502 #define CONFIG_SYS_IBAT7L 0x00000000
503 #define CONFIG_SYS_IBAT7U 0x00000000
508 #ifndef CONFIG_SYS_RAMBOOT
509 #define CONFIG_ENV_IS_IN_FLASH 1
510 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
511 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
513 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
514 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
516 #define CONFIG_ENV_SIZE 0x2000
518 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
519 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
525 #define CONFIG_BOOTP_BOOTFILESIZE
526 #define CONFIG_BOOTP_BOOTPATH
527 #define CONFIG_BOOTP_GATEWAY
528 #define CONFIG_BOOTP_HOSTNAME
532 * Command line configuration.
534 #include <config_cmd_default.h>
536 #define CONFIG_CMD_PING
537 #define CONFIG_CMD_I2C
538 #define CONFIG_CMD_REGINFO
540 #if defined(CONFIG_SYS_RAMBOOT)
541 #undef CONFIG_CMD_ENV
544 #if defined(CONFIG_PCI)
545 #define CONFIG_CMD_PCI
546 #define CONFIG_CMD_SCSI
547 #define CONFIG_CMD_EXT2
548 #define CONFIG_CMD_USB
552 #undef CONFIG_WATCHDOG /* watchdog disabled */
555 * Miscellaneous configurable options
557 #define CONFIG_SYS_LONGHELP /* undef to save memory */
558 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
559 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
560 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
562 #if defined(CONFIG_CMD_KGDB)
563 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
565 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
568 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
569 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
571 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
574 * For booting Linux, the board info and command line data
575 * have to be in the first 8 MB of memory, since this is
576 * the maximum mapped by the Linux kernel during initialization.
578 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
581 * Internal Definitions
585 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
586 #define BOOTFLAG_WARM 0x02 /* Software reboot */
588 #if defined(CONFIG_CMD_KGDB)
589 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
590 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
594 * Environment Configuration
597 /* The mac addresses for all ethernet interface */
598 #if defined(CONFIG_TSEC_ENET)
599 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
600 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
601 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
602 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
605 #define CONFIG_HAS_ETH0 1
606 #define CONFIG_HAS_ETH1 1
607 #define CONFIG_HAS_ETH2 1
608 #define CONFIG_HAS_ETH3 1
610 #define CONFIG_IPADDR 192.168.1.100
612 #define CONFIG_HOSTNAME unknown
613 #define CONFIG_ROOTPATH /opt/nfsroot
614 #define CONFIG_BOOTFILE uImage
615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
617 #define CONFIG_SERVERIP 192.168.1.1
618 #define CONFIG_GATEWAYIP 192.168.1.1
619 #define CONFIG_NETMASK 255.255.255.0
621 /* default location for tftp and bootm */
622 #define CONFIG_LOADADDR 1000000
624 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
625 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
627 #define CONFIG_BAUDRATE 115200
629 #define CONFIG_EXTRA_ENV_SETTINGS \
631 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
632 "tftpflash=tftpboot $loadaddr $uboot; " \
633 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
634 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
635 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
636 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
637 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
638 "consoledev=ttyS0\0" \
639 "ramdiskaddr=2000000\0" \
640 "ramdiskfile=your.ramdisk.u-boot\0" \
642 "fdtfile=mpc8641_hpcn.dtb\0" \
643 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
644 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
648 #define CONFIG_NFSBOOTCOMMAND \
649 "setenv bootargs root=/dev/nfs rw " \
650 "nfsroot=$serverip:$rootpath " \
651 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
652 "console=$consoledev,$baudrate $othbootargs;" \
653 "tftp $loadaddr $bootfile;" \
654 "tftp $fdtaddr $fdtfile;" \
655 "bootm $loadaddr - $fdtaddr"
657 #define CONFIG_RAMBOOTCOMMAND \
658 "setenv bootargs root=/dev/ram rw " \
659 "console=$consoledev,$baudrate $othbootargs;" \
660 "tftp $ramdiskaddr $ramdiskfile;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr $ramdiskaddr $fdtaddr"
665 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
667 #endif /* __CONFIG_H */