2 * Copyright 2006 Freescale Semiconductor.
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MPC8641HPCN board configuration file
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx 1 /* MPC86xx */
37 #define CONFIG_MPC8641 1 /* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
42 #define CONFIG_ADDR_MAP 1 /* Use addr map */
45 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
48 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
51 * virtual address to be used for temporary mappings. There
52 * should be 128k free at this VA.
54 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
57 * set this to enable Rapid IO. PCI and RIO are mutually exclusive
59 /*#define CONFIG_RIO 1*/
61 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
62 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
63 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
64 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
65 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
70 #define CONFIG_TSEC_ENET /* tsec ethernet support */
71 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
74 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
76 #define CONFIG_ALTIVEC 1
79 * L2CR setup -- make sure this is right for your board!
83 #define L2_ENABLE (L2CR_L2E)
85 #ifndef CONFIG_SYS_CLK_FREQ
87 extern unsigned long get_board_sys_clk(unsigned long dummy);
89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
92 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
94 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
95 #define CONFIG_SYS_MEMTEST_END 0x00400000
98 * With the exception of PCI Memory and Rapid IO, most devices will simply
99 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
100 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
102 #ifdef CONFIG_PHYS_64BIT
103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
105 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
109 * Base addresses -- Note these are effective addresses where the
110 * actual resources get mapped (not physical addresses)
112 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
113 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
114 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
116 /* Physical addresses */
117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
120 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \
121 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
123 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
124 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
127 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
128 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
133 #define CONFIG_FSL_DDR2
134 #undef CONFIG_FSL_DDR_INTERACTIVE
135 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
136 #define CONFIG_DDR_SPD
138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
139 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
144 #define CONFIG_VERY_BIG_RAM
146 #define MPC86xx_DDR_SDRAM_CLK_CNTL
148 #define CONFIG_NUM_DDR_CONTROLLERS 2
149 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
150 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
153 * I2C addresses of SPD EEPROMs
155 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
156 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
157 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
158 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
162 * These are used when DDR doesn't use SPD.
164 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
165 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
166 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
167 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
168 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
169 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
170 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
171 #define CONFIG_SYS_DDR_MODE_1 0x00480432
172 #define CONFIG_SYS_DDR_MODE_2 0x00000000
173 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
174 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
175 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
176 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
177 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
178 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
179 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
181 #define CONFIG_ID_EEPROM
182 #define CONFIG_SYS_I2C_EEPROM_NXID
183 #define CONFIG_ID_EEPROM
184 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
185 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
187 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
188 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
189 | CONFIG_SYS_PHYS_ADDR_HIGH)
191 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
193 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
194 | 0x00001001) /* port size 16bit */
195 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
197 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
198 | 0x00001001) /* port size 16bit */
199 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
201 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
202 | 0x00000801) /* port size 8bit */
203 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
206 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
207 * The PIXIS and CF by themselves aren't large enough to take up the 128k
208 * required for the smallest BAT mapping, so there's a 64k hole.
210 #define CONFIG_SYS_LBC_BASE 0xffde0000
211 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
212 | CONFIG_SYS_PHYS_ADDR_HIGH)
214 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
215 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
216 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
217 #define PIXIS_SIZE 0x00008000 /* 32k */
218 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
219 #define PIXIS_VER 0x1 /* Board version at offset 1 */
220 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
221 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
222 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
223 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
224 #define PIXIS_VCTL 0x10 /* VELA Control Register */
225 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
226 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
227 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
228 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
229 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
230 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
231 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
232 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
234 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
235 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
236 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
239 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
241 #undef CONFIG_SYS_FLASH_CHECKSUM
242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
244 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
245 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
247 #define CONFIG_FLASH_CFI_DRIVER
248 #define CONFIG_SYS_FLASH_CFI
249 #define CONFIG_SYS_FLASH_EMPTY_INFO
251 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
252 #define CONFIG_SYS_RAMBOOT
254 #undef CONFIG_SYS_RAMBOOT
257 #if defined(CONFIG_SYS_RAMBOOT)
258 #undef CONFIG_SPD_EEPROM
259 #define CONFIG_SYS_SDRAM_SIZE 256
262 #undef CONFIG_CLOCKS_IN_MHZ
264 #define CONFIG_SYS_INIT_RAM_LOCK 1
265 #ifndef CONFIG_SYS_INIT_RAM_LOCK
266 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
268 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
270 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
272 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
273 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
276 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
277 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
280 #define CONFIG_CONS_INDEX 1
281 #undef CONFIG_SERIAL_SOFTWARE_FIFO
282 #define CONFIG_SYS_NS16550
283 #define CONFIG_SYS_NS16550_SERIAL
284 #define CONFIG_SYS_NS16550_REG_SIZE 1
285 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
287 #define CONFIG_SYS_BAUDRATE_TABLE \
288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
293 /* Use the HUSH parser */
294 #define CONFIG_SYS_HUSH_PARSER
295 #ifdef CONFIG_SYS_HUSH_PARSER
296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
300 * Pass open firmware flat tree to kernel
302 #define CONFIG_OF_LIBFDT 1
303 #define CONFIG_OF_BOARD_SETUP 1
304 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
307 #define CONFIG_SYS_64BIT_VSPRINTF 1
308 #define CONFIG_SYS_64BIT_STRTOUL 1
313 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
314 #define CONFIG_HARD_I2C /* I2C with hardware support*/
315 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
316 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
317 #define CONFIG_SYS_I2C_SLAVE 0x7F
318 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
319 #define CONFIG_SYS_I2C_OFFSET 0x3100
324 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
328 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
330 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
334 * Addresses are mapped 1-1.
337 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
338 #ifdef CONFIG_PHYS_64BIT
339 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
340 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
342 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT
343 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT
345 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
346 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
347 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
348 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
349 | CONFIG_SYS_PHYS_ADDR_HIGH)
350 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */
353 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
354 #define _IO_BASE 0x00000000
356 #ifdef CONFIG_PHYS_64BIT
358 * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
359 * This will increase the amount of PCI address space available for
362 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS
364 #define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \
365 + CONFIG_SYS_PCI1_MEM_SIZE)
367 #define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \
368 + CONFIG_SYS_PCI1_MEM_SIZE)
369 #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
370 + CONFIG_SYS_PCI1_MEM_SIZE)
371 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
372 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
373 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
374 + CONFIG_SYS_PCI1_IO_SIZE)
375 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
376 + CONFIG_SYS_PCI1_IO_SIZE)
377 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
379 #if defined(CONFIG_PCI)
381 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
383 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
385 #define CONFIG_NET_MULTI
386 #define CONFIG_PCI_PNP /* do pci plug-and-play */
388 #define CONFIG_RTL8139
390 #undef CONFIG_EEPRO100
393 /************************************************************
395 ************************************************************/
396 #define CONFIG_PCI_OHCI 1
397 #define CONFIG_USB_OHCI_NEW 1
398 #define CONFIG_USB_KEYBOARD 1
399 #define CONFIG_SYS_DEVICE_DEREGISTER
400 #define CONFIG_SYS_USB_EVENT_POLL 1
401 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
402 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
403 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
405 /*PCIE video card used*/
406 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
408 /*PCI video card used*/
409 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
414 #if defined(CONFIG_VIDEO)
415 #define CONFIG_BIOSEMU
416 #define CONFIG_CFB_CONSOLE
417 #define CONFIG_VIDEO_SW_CURSOR
418 #define CONFIG_VGA_AS_SINGLE_DEVICE
419 #define CONFIG_ATI_RADEON_FB
420 #define CONFIG_VIDEO_LOGO
421 /*#define CONFIG_CONSOLE_CURSOR*/
422 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
425 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
427 #define CONFIG_DOS_PARTITION
428 #define CONFIG_SCSI_AHCI
430 #ifdef CONFIG_SCSI_AHCI
431 #define CONFIG_SATA_ULI5288
432 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
433 #define CONFIG_SYS_SCSI_MAX_LUN 1
434 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
435 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
438 #define CONFIG_MPC86XX_PCI2
440 #endif /* CONFIG_PCI */
442 #if defined(CONFIG_TSEC_ENET)
444 #ifndef CONFIG_NET_MULTI
445 #define CONFIG_NET_MULTI 1
448 #define CONFIG_MII 1 /* MII PHY management */
450 #define CONFIG_TSEC1 1
451 #define CONFIG_TSEC1_NAME "eTSEC1"
452 #define CONFIG_TSEC2 1
453 #define CONFIG_TSEC2_NAME "eTSEC2"
454 #define CONFIG_TSEC3 1
455 #define CONFIG_TSEC3_NAME "eTSEC3"
456 #define CONFIG_TSEC4 1
457 #define CONFIG_TSEC4_NAME "eTSEC4"
459 #define TSEC1_PHY_ADDR 0
460 #define TSEC2_PHY_ADDR 1
461 #define TSEC3_PHY_ADDR 2
462 #define TSEC4_PHY_ADDR 3
463 #define TSEC1_PHYIDX 0
464 #define TSEC2_PHYIDX 0
465 #define TSEC3_PHYIDX 0
466 #define TSEC4_PHYIDX 0
467 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
468 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
469 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
470 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
472 #define CONFIG_ETHPRIME "eTSEC1"
474 #endif /* CONFIG_TSEC_ENET */
476 /* Contort an addr into the format needed for BATs */
477 #ifdef CONFIG_PHYS_64BIT
478 #define BAT_PHYS_ADDR(x) ((unsigned long) \
479 ((x & 0x00000000ffffffffULL) | \
480 ((x & 0x0000000e00000000ULL) >> 24) | \
481 ((x & 0x0000000100000000ULL) >> 30)))
483 #define BAT_PHYS_ADDR(x) (x)
487 /* Put high physical address bits into the BAT format */
488 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
489 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
494 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
495 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
496 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
497 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
500 * BAT1 LBC (PIXIS/CF)
502 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
503 | BATL_PP_RW | BATL_CACHEINHIBIT | \
505 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
507 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
508 | BATL_PP_RW | BATL_MEMCOHERENCE)
509 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
512 * BAT2 PCI1 and PCI1 MEM
514 * BAT2 Rapidio Memory
517 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
518 | BATL_PP_RW | BATL_CACHEINHIBIT \
519 | BATL_GUARDEDSTORAGE)
520 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
522 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
523 | BATL_PP_RW | BATL_CACHEINHIBIT)
524 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
525 #else /* CONFIG_RIO */
526 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
527 | BATL_PP_RW | BATL_CACHEINHIBIT | \
529 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
531 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
532 | BATL_PP_RW | BATL_CACHEINHIBIT)
534 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
535 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
536 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
537 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
538 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
543 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs
544 * instead. The assembler chokes on ULL.
546 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
547 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
548 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
549 | BATL_PP_RW | BATL_CACHEINHIBIT \
550 | BATL_GUARDEDSTORAGE)
551 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
553 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
554 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
555 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
556 | BATL_PP_RW | BATL_CACHEINHIBIT)
557 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
559 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
560 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
561 | BATL_PP_RW | BATL_CACHEINHIBIT \
562 | BATL_GUARDEDSTORAGE)
563 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
564 | BATU_BL_1M | BATU_VS | BATU_VP)
565 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
566 | BATL_PP_RW | BATL_CACHEINHIBIT)
567 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
571 * BAT4 PCI1_IO and PCI2_IO
573 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
574 | BATL_PP_RW | BATL_CACHEINHIBIT \
575 | BATL_GUARDEDSTORAGE)
576 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
578 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
579 | BATL_PP_RW | BATL_CACHEINHIBIT)
580 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
583 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
585 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
586 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
587 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
588 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
593 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
594 | BATL_PP_RW | BATL_CACHEINHIBIT \
595 | BATL_GUARDEDSTORAGE)
596 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
598 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
599 | BATL_PP_RW | BATL_MEMCOHERENCE)
600 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
602 /* Map the last 1M of flash where we're running from reset */
603 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
604 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
605 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
606 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
608 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
611 * BAT7 FREE - used later for tmp mappings
613 #define CONFIG_SYS_DBAT7L 0x00000000
614 #define CONFIG_SYS_DBAT7U 0x00000000
615 #define CONFIG_SYS_IBAT7L 0x00000000
616 #define CONFIG_SYS_IBAT7U 0x00000000
621 #ifndef CONFIG_SYS_RAMBOOT
622 #define CONFIG_ENV_IS_IN_FLASH 1
623 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
624 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
626 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
627 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
629 #define CONFIG_ENV_SIZE 0x2000
631 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
632 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
638 #define CONFIG_BOOTP_BOOTFILESIZE
639 #define CONFIG_BOOTP_BOOTPATH
640 #define CONFIG_BOOTP_GATEWAY
641 #define CONFIG_BOOTP_HOSTNAME
645 * Command line configuration.
647 #include <config_cmd_default.h>
649 #define CONFIG_CMD_PING
650 #define CONFIG_CMD_I2C
651 #define CONFIG_CMD_REGINFO
653 #if defined(CONFIG_SYS_RAMBOOT)
654 #undef CONFIG_CMD_ENV
657 #if defined(CONFIG_PCI)
658 #define CONFIG_CMD_PCI
659 #define CONFIG_CMD_SCSI
660 #define CONFIG_CMD_EXT2
661 #define CONFIG_CMD_USB
665 #undef CONFIG_WATCHDOG /* watchdog disabled */
668 * Miscellaneous configurable options
670 #define CONFIG_SYS_LONGHELP /* undef to save memory */
671 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
672 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
673 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
675 #if defined(CONFIG_CMD_KGDB)
676 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
678 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
681 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
682 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
683 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
684 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
687 * For booting Linux, the board info and command line data
688 * have to be in the first 8 MB of memory, since this is
689 * the maximum mapped by the Linux kernel during initialization.
691 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
694 * Internal Definitions
698 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
699 #define BOOTFLAG_WARM 0x02 /* Software reboot */
701 #if defined(CONFIG_CMD_KGDB)
702 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
703 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
707 * Environment Configuration
710 /* The mac addresses for all ethernet interface */
711 #if defined(CONFIG_TSEC_ENET)
712 #define CONFIG_ETHADDR 00:E0:0C:00:00:01
713 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
714 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
715 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
718 #define CONFIG_HAS_ETH0 1
719 #define CONFIG_HAS_ETH1 1
720 #define CONFIG_HAS_ETH2 1
721 #define CONFIG_HAS_ETH3 1
723 #define CONFIG_IPADDR 192.168.1.100
725 #define CONFIG_HOSTNAME unknown
726 #define CONFIG_ROOTPATH /opt/nfsroot
727 #define CONFIG_BOOTFILE uImage
728 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
730 #define CONFIG_SERVERIP 192.168.1.1
731 #define CONFIG_GATEWAYIP 192.168.1.1
732 #define CONFIG_NETMASK 255.255.255.0
734 /* default location for tftp and bootm */
735 #define CONFIG_LOADADDR 1000000
737 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
738 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
740 #define CONFIG_BAUDRATE 115200
742 #define CONFIG_EXTRA_ENV_SETTINGS \
744 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
745 "tftpflash=tftpboot $loadaddr $uboot; " \
746 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
747 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
748 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
749 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
750 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
751 "consoledev=ttyS0\0" \
752 "ramdiskaddr=2000000\0" \
753 "ramdiskfile=your.ramdisk.u-boot\0" \
755 "fdtfile=mpc8641_hpcn.dtb\0" \
756 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
757 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
761 #define CONFIG_NFSBOOTCOMMAND \
762 "setenv bootargs root=/dev/nfs rw " \
763 "nfsroot=$serverip:$rootpath " \
764 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
765 "console=$consoledev,$baudrate $othbootargs;" \
766 "tftp $loadaddr $bootfile;" \
767 "tftp $fdtaddr $fdtfile;" \
768 "bootm $loadaddr - $fdtaddr"
770 #define CONFIG_RAMBOOTCOMMAND \
771 "setenv bootargs root=/dev/ram rw " \
772 "console=$consoledev,$baudrate $othbootargs;" \
773 "tftp $ramdiskaddr $ramdiskfile;" \
774 "tftp $loadaddr $bootfile;" \
775 "tftp $fdtaddr $fdtfile;" \
776 "bootm $loadaddr $ramdiskaddr $fdtaddr"
778 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
780 #endif /* __CONFIG_H */