2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * mpc8560ads board configuration file
28 * Please refer to doc/README.mpc85xx for more info.
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_MPC8560 1 /* MPC8560 specific */
42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
45 #define CONFIG_TSEC_ENET /* tsec ethernet support */
46 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
47 #define CONFIG_ENV_OVERWRITE
48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
49 #define CONFIG_DDR_ECC /* only for ECC DDR module */
50 #define CONFIG_DDR_DLL /* possible DLL fix needed */
51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
57 * Two valid values are:
61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
62 * is likely the desired value here, so that is now the default.
63 * The board, however, can run at 66MHz. In any event, this value
64 * must match the settings of some switches. Details can be found
65 * in the README.mpc85xxads.
68 #ifndef CONFIG_SYS_CLK_FREQ
69 #define CONFIG_SYS_CLK_FREQ 33000000
74 * These can be toggled for performance analysis, otherwise use default.
76 #define CONFIG_L2_CACHE /* toggle L2 cache */
77 #define CONFIG_BTB /* toggle branch predition */
78 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
82 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
84 #undef CFG_DRAM_TEST /* memory test, takes time */
85 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
86 #define CFG_MEMTEST_END 0x00400000
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
93 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
95 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
101 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
102 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
104 #if defined(CONFIG_SPD_EEPROM)
106 * Determine DDR configuration from I2C interface.
108 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
112 * Manually set up DDR parameters
114 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
115 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
116 #define CFG_DDR_CS0_CONFIG 0x80000002
117 #define CFG_DDR_TIMING_1 0x37344321
118 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
119 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
120 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
121 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
126 * SDRAM on the Local Bus
128 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
129 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
131 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
132 #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
134 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
135 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
136 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
137 #undef CFG_FLASH_CHECKSUM
138 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
144 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
151 #undef CONFIG_CLOCKS_IN_MHZ
155 * Local Bus Definitions
159 * Base Register 2 and Option Register 2 configure SDRAM.
160 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
163 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
164 * port-size = 32-bits = BR2[19:20] = 11
165 * no parity checking = BR2[21:22] = 00
166 * SDRAM for MSEL = BR2[24:26] = 011
169 * 0 4 8 12 16 20 24 28
170 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
172 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
173 * FIXME: the top 17 bits of BR2.
176 #define CFG_BR2_PRELIM 0xf0001861
179 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
182 * 64MB mask for AM, OR2[0:7] = 1111 1100
183 * XAM, OR2[17:18] = 11
184 * 9 columns OR2[19-21] = 010
185 * 13 rows OR2[23-25] = 100
186 * EAD set for extra time OR[31] = 1
188 * 0 4 8 12 16 20 24 28
189 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
192 #define CFG_OR2_PRELIM 0xfc006901
194 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
195 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
196 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
197 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
202 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
203 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
204 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
205 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
206 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
207 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
208 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
209 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
210 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
211 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
212 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
213 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
214 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
215 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
216 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
218 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
219 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
220 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
221 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
222 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
223 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
224 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
225 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
227 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
228 | CFG_LBC_LSDMR_RFCR5 \
229 | CFG_LBC_LSDMR_PRETOACT3 \
230 | CFG_LBC_LSDMR_ACTTORW3 \
231 | CFG_LBC_LSDMR_BL8 \
232 | CFG_LBC_LSDMR_WRC2 \
233 | CFG_LBC_LSDMR_CL3 \
234 | CFG_LBC_LSDMR_RFEN \
238 * SDRAM Controller configuration sequence.
240 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
241 | CFG_LBC_LSDMR_OP_PCHALL)
242 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
243 | CFG_LBC_LSDMR_OP_ARFRSH)
244 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
245 | CFG_LBC_LSDMR_OP_ARFRSH)
246 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
247 | CFG_LBC_LSDMR_OP_MRW)
248 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
249 | CFG_LBC_LSDMR_OP_NORMAL)
253 * 32KB, 8-bit wide for ADS config reg
255 #define CFG_BR4_PRELIM 0xf8000801
256 #define CFG_OR4_PRELIM 0xffffe1f1
257 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
259 #define CONFIG_L1_INIT_RAM
260 #define CFG_INIT_RAM_LOCK 1
261 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
262 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
264 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
265 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
266 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
268 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
269 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
272 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
273 #undef CONFIG_CONS_NONE /* define if console on something else */
274 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
276 #define CONFIG_BAUDRATE 115200
278 #define CFG_BAUDRATE_TABLE \
279 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
281 /* Use the HUSH parser */
282 #define CFG_HUSH_PARSER
283 #ifdef CFG_HUSH_PARSER
284 #define CFG_PROMPT_HUSH_PS2 "> "
288 #define CONFIG_HARD_I2C /* I2C with hardware support*/
289 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
290 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
291 #define CFG_I2C_SLAVE 0x7F
292 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
295 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
296 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
297 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
301 * Addresses are mapped 1-1.
303 #define CFG_PCI1_MEM_BASE 0x80000000
304 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
305 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
306 #define CFG_PCI1_IO_BASE 0xe2000000
307 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
308 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
310 #if defined(CONFIG_PCI)
312 #define CONFIG_NET_MULTI
313 #define CONFIG_PCI_PNP /* do pci plug-and-play */
315 #undef CONFIG_EEPRO100
318 #if !defined(CONFIG_PCI_PNP)
319 #define PCI_ENET0_IOADDR 0xe0000000
320 #define PCI_ENET0_MEMADDR 0xe0000000
321 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
324 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
325 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
327 #endif /* CONFIG_PCI */
330 #if defined(CONFIG_TSEC_ENET)
332 #ifndef CONFIG_NET_MULTI
333 #define CONFIG_NET_MULTI 1
336 #define CONFIG_MII 1 /* MII PHY management */
337 #define CONFIG_MPC85XX_TSEC1 1
338 #define CONFIG_MPC85XX_TSEC2 1
339 #undef CONFIG_MPC85XX_FEC
340 #define TSEC1_PHY_ADDR 0
341 #define TSEC2_PHY_ADDR 1
342 #define TSEC1_PHYIDX 0
343 #define TSEC2_PHYIDX 0
344 #define CONFIG_ETHPRIME "MOTO ENET0"
346 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
348 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
349 #undef CONFIG_ETHER_NONE /* define if ether on something else */
350 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
352 #if (CONFIG_ETHER_INDEX == 2)
356 * - Select bus for bd/buffers
359 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
360 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
361 #define CFG_CPMFCR_RAMTYPE 0
362 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
363 #define FETH2_RST 0x01
364 #elif (CONFIG_ETHER_INDEX == 3)
365 /* need more definitions here for FE3 */
366 #define FETH3_RST 0x80
367 #endif /* CONFIG_ETHER_INDEX */
369 #define CONFIG_MII /* MII PHY management */
370 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
373 * GPIO pins used for bit-banged MII communications
375 #define MDIO_PORT 2 /* Port C */
376 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
377 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
378 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
380 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
381 else iop->pdat &= ~0x00400000
383 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
384 else iop->pdat &= ~0x00200000
386 #define MIIDELAY udelay(1)
395 #define CFG_ENV_IS_IN_FLASH 1
396 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
397 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
398 #define CFG_ENV_SIZE 0x2000
400 #define CFG_NO_FLASH 1 /* Flash is not usable now */
401 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
402 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
403 #define CFG_ENV_SIZE 0x2000
406 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
407 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
409 #if defined(CFG_RAMBOOT)
410 #if defined(CONFIG_PCI)
411 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
418 #elif defined(CONFIG_TSEC_ENET)
419 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
423 #elif defined(CONFIG_ETHER_ON_FCC)
424 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
431 #if defined(CONFIG_PCI)
432 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
436 #elif defined(CONFIG_TSEC_ENET)
437 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
440 #elif defined(CONFIG_ETHER_ON_FCC)
441 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
448 #include <cmd_confdefs.h>
450 #undef CONFIG_WATCHDOG /* watchdog disabled */
453 * Miscellaneous configurable options
455 #define CFG_LONGHELP /* undef to save memory */
456 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
457 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
459 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
460 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
462 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
465 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
466 #define CFG_MAXARGS 16 /* max number of command args */
467 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
468 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
471 * For booting Linux, the board info and command line data
472 * have to be in the first 8 MB of memory, since this is
473 * the maximum mapped by the Linux kernel during initialization.
475 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
477 /* Cache Configuration */
478 #define CFG_DCACHE_SIZE 32768
479 #define CFG_CACHELINE_SIZE 32
480 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
481 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
485 * Internal Definitions
489 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
490 #define BOOTFLAG_WARM 0x02 /* Software reboot */
492 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
493 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
494 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
499 * Environment Configuration
502 /* The mac addresses for all ethernet interface */
503 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
504 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
505 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
506 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
509 #define CONFIG_IPADDR 192.168.1.253
511 #define CONFIG_HOSTNAME unknown
512 #define CONFIG_ROOTPATH /nfsroot
513 #define CONFIG_BOOTFILE your.uImage
515 #define CONFIG_SERVERIP 192.168.1.1
516 #define CONFIG_GATEWAYIP 192.168.1.1
517 #define CONFIG_NETMASK 255.255.255.0
519 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
521 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
522 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
524 #define CONFIG_BAUDRATE 115200
526 #define CONFIG_EXTRA_ENV_SETTINGS \
528 "consoledev=ttyS0\0" \
529 "ramdiskaddr=400000\0" \
530 "ramdiskfile=your.ramdisk.u-boot\0"
532 #define CONFIG_NFSBOOTCOMMAND \
533 "setenv bootargs root=/dev/nfs rw " \
534 "nfsroot=$serverip:$rootpath " \
535 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $loadaddr $bootfile;" \
540 #define CONFIG_RAMBOOTCOMMAND \
541 "setenv bootargs root=/dev/ram rw " \
542 "console=$consoledev,$baudrate $othbootargs;" \
543 "tftp $ramdiskaddr $ramdiskfile;" \
544 "tftp $loadaddr $bootfile;" \
545 "bootm $loadaddr $ramdiskaddr"
547 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
549 #endif /* __CONFIG_H */