2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8544ds board configuration file
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE 1 /* BOOKE */
32 #define CONFIG_E500 1 /* BOOKE e500 family */
33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8544 1
35 #define CONFIG_MPC8544DS 1
37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
38 #define CONFIG_PCI1 1 /* PCI controller 1 */
39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
44 #define CONFIG_TSEC_ENET /* tsec ethernet support */
45 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
48 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
50 #define CONFIG_DDR_ECC /* only for ECC DDR module */
51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
54 #define CONFIG_DDR_ECC_CMD
55 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58 * When initializing flash, if we cannot find the manufacturer ID,
59 * assume this is the AMD flash associated with the CDS board.
60 * This allows booting from a promjet.
62 #define CONFIG_ASSUME_AMD_FLASH
64 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
67 extern unsigned long get_board_sys_clk(unsigned long dummy);
69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_L2_CACHE /* toggle L2 cache */
75 #define CONFIG_BTB /* toggle branch predition */
76 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
77 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
80 * Only possible on E500 Version 2 or newer cores.
82 #define CONFIG_ENABLE_36BIT_PHYS 1
84 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
86 #undef CFG_DRAM_TEST /* memory test, takes time */
87 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
88 #define CFG_MEMTEST_END 0x00400000
89 #define CFG_ALT_MEMTEST
90 #define CONFIG_PANIC_HANG /* do not reset board on panic */
93 * Base addresses -- Note these are effective addresses where the
94 * actual resources get mapped (not physical addresses)
96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
97 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
98 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
100 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
101 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
102 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
103 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
108 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
109 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
111 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
114 * Make sure required options are set
116 #ifndef CONFIG_SPD_EEPROM
117 #error ("CONFIG_SPD_EEPROM is required")
120 #undef CONFIG_CLOCKS_IN_MHZ
125 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
127 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
129 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
131 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
132 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
136 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
137 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
139 * Localbus non-cacheable
141 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
142 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
143 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
148 * Local Bus Definitions
150 #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
152 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
154 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
156 #define CFG_BR0_PRELIM 0xff801001
157 #define CFG_BR1_PRELIM 0xfe801001
159 #define CFG_OR0_PRELIM 0xff806e65
160 #define CFG_OR1_PRELIM 0xff806e65
162 #define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
164 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
165 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
166 #undef CFG_FLASH_CHECKSUM
167 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
168 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
170 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
172 #define CFG_FLASH_CFI_DRIVER
173 #define CFG_FLASH_CFI
174 #define CFG_FLASH_EMPTY_INFO
176 #define CFG_LBC_NONCACHE_BASE 0xf8000000
178 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
179 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
181 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
182 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
184 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
185 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */
186 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
187 #define PIXIS_VER 0x1 /* Board version at offset 1 */
188 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
189 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
190 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
192 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
193 #define PIXIS_VCTL 0x10 /* VELA Control Register */
194 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
195 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
196 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
197 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
198 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
199 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
200 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
201 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
204 /* define to use L1 as initial stack */
205 #define CONFIG_L1_INIT_RAM 1
206 #define CFG_INIT_L1_LOCK 1
207 #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */
208 #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
210 /* define to use L2SRAM as initial stack */
211 #undef CONFIG_L2_INIT_RAM
212 #define CFG_INIT_L2_ADDR 0xf8fc0000
213 #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
215 #ifdef CONFIG_L1_INIT_RAM
216 #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR
217 #define CFG_INIT_RAM_END CFG_INIT_L1_END
219 #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR
220 #define CFG_INIT_RAM_END CFG_INIT_L2_END
223 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
224 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
225 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
227 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
228 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
230 /* Serial Port - controlled on board with jumper J8
234 #define CONFIG_CONS_INDEX 1
235 #undef CONFIG_SERIAL_SOFTWARE_FIFO
237 #define CFG_NS16550_SERIAL
238 #define CFG_NS16550_REG_SIZE 1
239 #define CFG_NS16550_CLK get_bus_freq(0)
241 #define CFG_BAUDRATE_TABLE \
242 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
244 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
245 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
247 /* Use the HUSH parser */
248 #define CFG_HUSH_PARSER
249 #ifdef CFG_HUSH_PARSER
250 #define CFG_PROMPT_HUSH_PS2 "> "
253 /* pass open firmware flat tree */
254 #define CONFIG_OF_LIBFDT 1
255 #define CONFIG_OF_BOARD_SETUP 1
256 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
259 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
260 #define CONFIG_HARD_I2C /* I2C with hardware support */
261 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
262 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
263 #define CFG_I2C_EEPROM_ADDR 0x57
264 #define CFG_I2C_SLAVE 0x7F
265 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
266 #define CFG_I2C_OFFSET 0x3100
270 * Memory space is mapped 1-1, but I/O space must start from 0.
272 #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
273 #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
275 #define CFG_PCI1_MEM_BASE 0xc0000000
276 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
277 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
278 #define CFG_PCI1_IO_BASE 0x00000000
279 #define CFG_PCI1_IO_PHYS 0xe1000000
280 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
282 /* PCI view of System Memory */
283 #define CFG_PCI_MEMORY_BUS 0x00000000
284 #define CFG_PCI_MEMORY_PHYS 0x00000000
285 #define CFG_PCI_MEMORY_SIZE 0x80000000
287 /* controller 2, Slot 1, tgtid 1, Base address 9000 */
288 #define CFG_PCIE2_MEM_BASE 0x80000000
289 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
290 #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
291 #define CFG_PCIE2_IO_BASE 0x00000000
292 #define CFG_PCIE2_IO_PHYS 0xe1010000
293 #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
295 /* controller 1, Slot 2,tgtid 2, Base address a000 */
296 #define CFG_PCIE1_MEM_BASE 0xa0000000
297 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
298 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
299 #define CFG_PCIE1_IO_BASE 0x00000000
300 #define CFG_PCIE1_IO_PHYS 0xe1020000
301 #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
303 /* controller 3, direct to uli, tgtid 3, Base address b000 */
304 #define CFG_PCIE3_MEM_BASE 0xb0000000
305 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
306 #define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
307 #define CFG_PCIE3_IO_BASE 0x00000000
308 #define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
309 #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
310 #define CFG_PCIE3_MEM_BASE2 0xb0200000
311 #define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
312 #define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
314 #if defined(CONFIG_PCI)
316 #define CONFIG_NET_MULTI
317 #define CONFIG_PCI_PNP /* do pci plug-and-play */
319 #undef CONFIG_EEPRO100
321 #define CONFIG_RTL8139
323 #ifdef CONFIG_RTL8139
324 /* This macro is used by RTL8139 but not defined in PPC architecture */
325 #define KSEG1ADDR(x) (x)
326 #define _IO_BASE 0x00000000
329 #ifndef CONFIG_PCI_PNP
330 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
331 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
332 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
335 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
336 #define CONFIG_DOS_PARTITION
337 #define CONFIG_SCSI_AHCI
339 #ifdef CONFIG_SCSI_AHCI
340 #define CONFIG_SATA_ULI5288
341 #define CFG_SCSI_MAX_SCSI_ID 4
342 #define CFG_SCSI_MAX_LUN 1
343 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
344 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
347 #endif /* CONFIG_PCI */
350 #if defined(CONFIG_TSEC_ENET)
352 #ifndef CONFIG_NET_MULTI
353 #define CONFIG_NET_MULTI 1
356 #define CONFIG_MII 1 /* MII PHY management */
357 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
358 #define CONFIG_TSEC1 1
359 #define CONFIG_TSEC1_NAME "eTSEC1"
360 #define CONFIG_TSEC3 1
361 #define CONFIG_TSEC3_NAME "eTSEC3"
363 #define TSEC1_PHY_ADDR 0
364 #define TSEC3_PHY_ADDR 1
366 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
367 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
369 #define TSEC1_PHYIDX 0
370 #define TSEC3_PHYIDX 0
372 #define CONFIG_ETHPRIME "eTSEC1"
374 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
375 #endif /* CONFIG_TSEC_ENET */
380 #define CFG_ENV_IS_IN_FLASH 1
381 #if CFG_MONITOR_BASE > 0xfff80000
382 #define CFG_ENV_ADDR 0xfff80000
384 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
386 #define CFG_ENV_SIZE 0x2000
387 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
389 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
390 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
395 #define CONFIG_BOOTP_BOOTFILESIZE
396 #define CONFIG_BOOTP_BOOTPATH
397 #define CONFIG_BOOTP_GATEWAY
398 #define CONFIG_BOOTP_HOSTNAME
402 * Command line configuration.
404 #include <config_cmd_default.h>
406 #define CONFIG_CMD_PING
407 #define CONFIG_CMD_I2C
408 #define CONFIG_CMD_MII
410 #if defined(CONFIG_PCI)
411 #define CONFIG_CMD_PCI
412 #define CONFIG_CMD_BEDBUG
413 #define CONFIG_CMD_NET
414 #define CONFIG_CMD_SCSI
415 #define CONFIG_CMD_EXT2
419 #undef CONFIG_WATCHDOG /* watchdog disabled */
422 * Miscellaneous configurable options
424 #define CFG_LONGHELP /* undef to save memory */
425 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
426 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
427 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
428 #if defined(CONFIG_CMD_KGDB)
429 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
431 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
433 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
434 #define CFG_MAXARGS 16 /* max number of command args */
435 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
436 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
439 * For booting Linux, the board info and command line data
440 * have to be in the first 8 MB of memory, since this is
441 * the maximum mapped by the Linux kernel during initialization.
443 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
445 /* Cache Configuration */
446 #define CFG_DCACHE_SIZE 32768
447 #define CFG_CACHELINE_SIZE 32
448 #if defined(CONFIG_CMD_KGDB)
449 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
453 * Internal Definitions
457 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
458 #define BOOTFLAG_WARM 0x02 /* Software reboot */
460 #if defined(CONFIG_CMD_KGDB)
461 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
462 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
466 * Environment Configuration
469 /* The mac addresses for all ethernet interface */
470 #if defined(CONFIG_TSEC_ENET)
471 #define CONFIG_HAS_ETH0
472 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
473 #define CONFIG_HAS_ETH1
474 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
477 #define CONFIG_IPADDR 192.168.1.251
479 #define CONFIG_HOSTNAME 8544ds_unknown
480 #define CONFIG_ROOTPATH /nfs/mpc85xx
481 #define CONFIG_BOOTFILE 8544ds/uImage.uboot
482 #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
484 #define CONFIG_SERVERIP 192.168.1.1
485 #define CONFIG_GATEWAYIP 192.168.1.1
486 #define CONFIG_NETMASK 255.255.0.0
488 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
490 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
491 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
493 #define CONFIG_BAUDRATE 115200
495 #define CONFIG_EXTRA_ENV_SETTINGS \
497 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
498 "tftpflash=tftpboot $loadaddr $uboot; " \
499 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
500 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
501 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
502 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
503 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
504 "consoledev=ttyS0\0" \
505 "ramdiskaddr=2000000\0" \
506 "ramdiskfile=8544ds/ramdisk.uboot\0" \
508 "fdtfile=8544ds/mpc8544ds.dtb\0" \
511 #define CONFIG_NFSBOOTCOMMAND \
512 "setenv bootargs root=/dev/nfs rw " \
513 "nfsroot=$serverip:$rootpath " \
514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "tftp $loadaddr $bootfile;" \
517 "tftp $fdtaddr $fdtfile;" \
518 "bootm $loadaddr - $fdtaddr"
520 #define CONFIG_RAMBOOTCOMMAND \
521 "setenv bootargs root=/dev/ram rw " \
522 "console=$consoledev,$baudrate $othbootargs;" \
523 "tftp $ramdiskaddr $ramdiskfile;" \
524 "tftp $loadaddr $bootfile;" \
525 "tftp $fdtaddr $fdtfile;" \
526 "bootm $loadaddr $ramdiskaddr $fdtaddr"
528 #define CONFIG_BOOTCOMMAND \
529 "setenv bootargs root=/dev/$bdev rw " \
530 "console=$consoledev,$baudrate $othbootargs;" \
531 "tftp $loadaddr $bootfile;" \
532 "tftp $fdtaddr $fdtfile;" \
533 "bootm $loadaddr - $fdtaddr"
535 #endif /* __CONFIG_H */