2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8541cds board configuration file
26 * Please refer to doc/README.mpc85xxcds for more info.
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
36 #define CONFIG_CPM2 1 /* has CPM2 */
37 #define CONFIG_MPC8541 1 /* MPC8541 specific */
38 #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
41 #define CONFIG_TSEC_ENET /* tsec ethernet support */
42 #define CONFIG_ENV_OVERWRITE
44 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
46 #define CONFIG_FSL_VIA
47 #define CONFIG_FSL_CDS_EEPROM
50 * When initializing flash, if we cannot find the manufacturer ID,
51 * assume this is the AMD flash associated with the CDS board.
52 * This allows booting from a promjet.
54 #define CONFIG_ASSUME_AMD_FLASH
57 extern unsigned long get_clock_freq(void);
59 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
62 * These can be toggled for performance analysis, otherwise use default.
64 #define CONFIG_L2_CACHE /* toggle L2 cache */
65 #define CONFIG_BTB /* toggle branch predition */
66 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
68 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
69 #define CFG_MEMTEST_END 0x00400000
72 * Base addresses -- Note these are effective addresses where the
73 * actual resources get mapped (not physical addresses)
75 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
76 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
77 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
78 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
81 #define CONFIG_FSL_DDR1
82 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
83 #define CONFIG_DDR_SPD
84 #undef CONFIG_FSL_DDR_INTERACTIVE
86 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
88 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
89 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
91 #define CONFIG_NUM_DDR_CONTROLLERS 1
92 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
93 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
95 /* I2C addresses of SPD EEPROMs */
96 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
99 * Make sure required options are set
101 #ifndef CONFIG_SPD_EEPROM
102 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
105 #undef CONFIG_CLOCKS_IN_MHZ
108 * Local Bus Definitions
112 * FLASH on the Local Bus
113 * Two banks, 8M each, using the CFI driver.
114 * Boot from BR0/OR0 bank at 0xff00_0000
115 * Alternate BR1/OR1 bank at 0xff80_0000
118 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
119 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
120 * Port Size = 16 bits = BRx[19:20] = 10
121 * Use GPCM = BRx[24:26] = 000
122 * Valid = BRx[31] = 1
124 * 0 4 8 12 16 20 24 28
125 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
126 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
129 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
130 * Reserved ORx[17:18] = 11, confusion here?
132 * ACS = half cycle delay = ORx[21:22] = 11
133 * SCY = 6 = ORx[24:27] = 0110
134 * TRLX = use relaxed timing = ORx[29] = 1
135 * EAD = use external address latch delay = OR[31] = 1
137 * 0 4 8 12 16 20 24 28
138 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
141 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
143 #define CFG_BR0_PRELIM 0xff801001
144 #define CFG_BR1_PRELIM 0xff001001
146 #define CFG_OR0_PRELIM 0xff806e65
147 #define CFG_OR1_PRELIM 0xff806e65
149 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
150 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
151 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
152 #undef CFG_FLASH_CHECKSUM
153 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
156 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
158 #define CONFIG_FLASH_CFI_DRIVER
159 #define CFG_FLASH_CFI
160 #define CFG_FLASH_EMPTY_INFO
164 * SDRAM on the Local Bus
166 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
167 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
170 * Base Register 2 and Option Register 2 configure SDRAM.
171 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
174 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
175 * port-size = 32-bits = BR2[19:20] = 11
176 * no parity checking = BR2[21:22] = 00
177 * SDRAM for MSEL = BR2[24:26] = 011
180 * 0 4 8 12 16 20 24 28
181 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
183 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
184 * FIXME: the top 17 bits of BR2.
187 #define CFG_BR2_PRELIM 0xf0001861
190 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
193 * 64MB mask for AM, OR2[0:7] = 1111 1100
194 * XAM, OR2[17:18] = 11
195 * 9 columns OR2[19-21] = 010
196 * 13 rows OR2[23-25] = 100
197 * EAD set for extra time OR[31] = 1
199 * 0 4 8 12 16 20 24 28
200 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
203 #define CFG_OR2_PRELIM 0xfc006901
205 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
206 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
207 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
208 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
213 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
214 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
215 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
216 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
217 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
218 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
219 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
220 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
221 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
222 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
224 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
225 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
226 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
227 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
228 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
229 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
230 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
231 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
234 * Common settings for all Local Bus SDRAM commands.
235 * At run time, either BSMA1516 (for CPU 1.1)
236 * or BSMA1617 (for CPU 1.0) (old)
239 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
240 | CFG_LBC_LSDMR_PRETOACT7 \
241 | CFG_LBC_LSDMR_ACTTORW7 \
242 | CFG_LBC_LSDMR_BL8 \
243 | CFG_LBC_LSDMR_WRC4 \
244 | CFG_LBC_LSDMR_CL3 \
245 | CFG_LBC_LSDMR_RFEN \
249 * The CADMUS registers are connected to CS3 on CDS.
250 * The new memory map places CADMUS at 0xf8000000.
253 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
254 * port-size = 8-bits = BR[19:20] = 01
255 * no parity checking = BR[21:22] = 00
256 * GPMC for MSEL = BR[24:26] = 000
259 * 0 4 8 12 16 20 24 28
260 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
263 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
264 * disable buffer ctrl OR[19] = 0
268 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
272 * EAD extra time OR[31] = 1
274 * 0 4 8 12 16 20 24 28
275 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
278 #define CONFIG_FSL_CADMUS
280 #define CADMUS_BASE_ADDR 0xf8000000
281 #define CFG_BR3_PRELIM 0xf8000801
282 #define CFG_OR3_PRELIM 0xfff00ff7
284 #define CONFIG_L1_INIT_RAM
285 #define CFG_INIT_RAM_LOCK 1
286 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
287 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
289 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
290 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
291 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
293 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
294 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
297 #define CONFIG_CONS_INDEX 2
298 #undef CONFIG_SERIAL_SOFTWARE_FIFO
300 #define CFG_NS16550_SERIAL
301 #define CFG_NS16550_REG_SIZE 1
302 #define CFG_NS16550_CLK get_bus_freq(0)
304 #define CFG_BAUDRATE_TABLE \
305 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
307 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
308 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
310 /* Use the HUSH parser */
311 #define CFG_HUSH_PARSER
312 #ifdef CFG_HUSH_PARSER
313 #define CFG_PROMPT_HUSH_PS2 "> "
316 /* pass open firmware flat tree */
317 #define CONFIG_OF_LIBFDT 1
318 #define CONFIG_OF_BOARD_SETUP 1
319 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
321 #define CFG_64BIT_VSPRINTF 1
322 #define CFG_64BIT_STRTOUL 1
327 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
328 #define CONFIG_HARD_I2C /* I2C with hardware support*/
329 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
330 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
331 #define CFG_I2C_EEPROM_ADDR 0x57
332 #define CFG_I2C_SLAVE 0x7F
333 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
334 #define CFG_I2C_OFFSET 0x3000
338 * Memory space is mapped 1-1, but I/O space must start from 0.
340 #define CFG_PCI1_MEM_BASE 0x80000000
341 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
342 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
343 #define CFG_PCI1_IO_BASE 0x00000000
344 #define CFG_PCI1_IO_PHYS 0xe2000000
345 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
347 #define CFG_PCI2_MEM_BASE 0xa0000000
348 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
349 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
350 #define CFG_PCI2_IO_BASE 0x00000000
351 #define CFG_PCI2_IO_PHYS 0xe2100000
352 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
362 #if defined(CONFIG_PCI)
364 #define CONFIG_MPC85XX_PCI2
365 #define CONFIG_NET_MULTI
366 #define CONFIG_PCI_PNP /* do pci plug-and-play */
368 #undef CONFIG_EEPRO100
371 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
372 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
374 #endif /* CONFIG_PCI */
377 #if defined(CONFIG_TSEC_ENET)
379 #ifndef CONFIG_NET_MULTI
380 #define CONFIG_NET_MULTI 1
383 #define CONFIG_MII 1 /* MII PHY management */
384 #define CONFIG_TSEC1 1
385 #define CONFIG_TSEC1_NAME "TSEC0"
386 #define CONFIG_TSEC2 1
387 #define CONFIG_TSEC2_NAME "TSEC1"
388 #define TSEC1_PHY_ADDR 0
389 #define TSEC2_PHY_ADDR 1
390 #define TSEC1_PHYIDX 0
391 #define TSEC2_PHYIDX 0
392 #define TSEC1_FLAGS TSEC_GIGABIT
393 #define TSEC2_FLAGS TSEC_GIGABIT
395 /* Options are: TSEC[0-1] */
396 #define CONFIG_ETHPRIME "TSEC0"
398 #endif /* CONFIG_TSEC_ENET */
403 #define CFG_ENV_IS_IN_FLASH 1
404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
405 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
406 #define CFG_ENV_SIZE 0x2000
408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
409 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
414 #define CONFIG_BOOTP_BOOTFILESIZE
415 #define CONFIG_BOOTP_BOOTPATH
416 #define CONFIG_BOOTP_GATEWAY
417 #define CONFIG_BOOTP_HOSTNAME
421 * Command line configuration.
423 #include <config_cmd_default.h>
425 #define CONFIG_CMD_PING
426 #define CONFIG_CMD_I2C
427 #define CONFIG_CMD_MII
428 #define CONFIG_CMD_ELF
430 #if defined(CONFIG_PCI)
431 #define CONFIG_CMD_PCI
435 #undef CONFIG_WATCHDOG /* watchdog disabled */
438 * Miscellaneous configurable options
440 #define CFG_LONGHELP /* undef to save memory */
441 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
442 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
443 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
444 #if defined(CONFIG_CMD_KGDB)
445 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
447 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
449 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
450 #define CFG_MAXARGS 16 /* max number of command args */
451 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
452 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
455 * For booting Linux, the board info and command line data
456 * have to be in the first 8 MB of memory, since this is
457 * the maximum mapped by the Linux kernel during initialization.
459 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
462 * Internal Definitions
466 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
467 #define BOOTFLAG_WARM 0x02 /* Software reboot */
469 #if defined(CONFIG_CMD_KGDB)
470 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
471 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
475 * Environment Configuration
478 /* The mac addresses for all ethernet interface */
479 #if defined(CONFIG_TSEC_ENET)
480 #define CONFIG_HAS_ETH0
481 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
482 #define CONFIG_HAS_ETH1
483 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
484 #define CONFIG_HAS_ETH2
485 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
488 #define CONFIG_IPADDR 192.168.1.253
490 #define CONFIG_HOSTNAME unknown
491 #define CONFIG_ROOTPATH /nfsroot
492 #define CONFIG_BOOTFILE your.uImage
494 #define CONFIG_SERVERIP 192.168.1.1
495 #define CONFIG_GATEWAYIP 192.168.1.1
496 #define CONFIG_NETMASK 255.255.255.0
498 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
500 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
501 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
503 #define CONFIG_BAUDRATE 115200
505 #define CONFIG_EXTRA_ENV_SETTINGS \
507 "consoledev=ttyS1\0" \
508 "ramdiskaddr=600000\0" \
509 "ramdiskfile=your.ramdisk.u-boot\0" \
511 "fdtfile=your.fdt.dtb\0"
513 #define CONFIG_NFSBOOTCOMMAND \
514 "setenv bootargs root=/dev/nfs rw " \
515 "nfsroot=$serverip:$rootpath " \
516 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
517 "console=$consoledev,$baudrate $othbootargs;" \
518 "tftp $loadaddr $bootfile;" \
519 "tftp $fdtaddr $fdtfile;" \
520 "bootm $loadaddr - $fdtaddr"
522 #define CONFIG_RAMBOOTCOMMAND \
523 "setenv bootargs root=/dev/ram rw " \
524 "console=$consoledev,$baudrate $othbootargs;" \
525 "tftp $ramdiskaddr $ramdiskfile;" \
526 "tftp $loadaddr $bootfile;" \
527 "bootm $loadaddr $ramdiskaddr"
529 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
531 #endif /* __CONFIG_H */