2 * Copyright 2007-2009,2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8536ds board configuration file
30 #include "../board/freescale/common/ics307_clk.h"
33 #define CONFIG_PHYS_64BIT 1
37 #define CONFIG_NAND_U_BOOT 1
38 #define CONFIG_RAMBOOT_NAND 1
39 #ifdef CONFIG_NAND_SPL
40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000
44 #endif /* CONFIG_NAND_SPL */
48 #define CONFIG_RAMBOOT_SDCARD 1
49 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
52 #ifdef CONFIG_SPIFLASH
53 #define CONFIG_RAMBOOT_SPIFLASH 1
54 #define CONFIG_SYS_TEXT_BASE 0xf8f80000
57 #ifndef CONFIG_SYS_TEXT_BASE
58 #define CONFIG_SYS_TEXT_BASE 0xeff80000
61 #ifndef CONFIG_SYS_MONITOR_BASE
62 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
65 /* High Level Configuration Options */
66 #define CONFIG_BOOKE 1 /* BOOKE */
67 #define CONFIG_E500 1 /* BOOKE e500 family */
68 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
69 #define CONFIG_MPC8536 1
70 #define CONFIG_MPC8536DS 1
72 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
73 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
74 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
75 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
76 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
77 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
78 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
79 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
80 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
81 #define CONFIG_SYS_HAS_SERDES /* has SERDES */
83 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
84 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
86 #define CONFIG_TSEC_ENET /* tsec ethernet support */
87 #define CONFIG_ENV_OVERWRITE
89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
90 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
91 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
94 * These can be toggled for performance analysis, otherwise use default.
96 #define CONFIG_L2_CACHE /* toggle L2 cache */
97 #define CONFIG_BTB /* toggle branch predition */
99 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
101 #define CONFIG_ENABLE_36BIT_PHYS 1
103 #ifdef CONFIG_PHYS_64BIT
104 #define CONFIG_ADDR_MAP 1
105 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
108 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
109 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
110 #define CONFIG_PANIC_HANG /* do not reset board on panic */
113 * Config the L2 Cache as L2 SRAM
115 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
119 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
121 #define CONFIG_SYS_L2_SIZE (512 << 10)
122 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
125 * Base addresses -- Note these are effective addresses where the
126 * actual resources get mapped (not physical addresses)
128 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
132 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
134 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
136 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
137 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
139 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
143 #define CONFIG_VERY_BIG_RAM
144 #define CONFIG_FSL_DDR2
145 #undef CONFIG_FSL_DDR_INTERACTIVE
146 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
147 #define CONFIG_DDR_SPD
148 #undef CONFIG_DDR_DLL
150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
151 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156 #define CONFIG_NUM_DDR_CONTROLLERS 1
157 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
158 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
160 /* I2C addresses of SPD EEPROMs */
161 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
162 #define CONFIG_SYS_SPD_BUS_NUM 1
164 /* These are used when DDR doesn't use SPD. */
165 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
166 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
167 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
168 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
169 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
170 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
171 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
172 #define CONFIG_SYS_DDR_MODE_1 0x00480432
173 #define CONFIG_SYS_DDR_MODE_2 0x00000000
174 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
177 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
178 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
179 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
180 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
182 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
183 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
184 #define CONFIG_SYS_DDR_SBE 0x00010000
186 /* Make sure required options are set */
187 #ifndef CONFIG_SPD_EEPROM
188 #error ("CONFIG_SPD_EEPROM is required")
191 #undef CONFIG_CLOCKS_IN_MHZ
195 * Memory map -- xxx -this is wrong, needs updating
197 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
198 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
199 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
200 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
202 * Localbus cacheable (TBD)
203 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
205 * Localbus non-cacheable
206 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
207 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
208 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
209 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
210 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
211 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
215 * Local Bus Definitions
217 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
221 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
224 #define CONFIG_FLASH_BR_PRELIM \
225 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
227 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
229 #define CONFIG_SYS_BR1_PRELIM \
230 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
232 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
234 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
235 CONFIG_SYS_FLASH_BASE_PHYS }
236 #define CONFIG_SYS_FLASH_QUIET_TEST
237 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
239 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
240 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
241 #undef CONFIG_SYS_FLASH_CHECKSUM
242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
245 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
246 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
247 #define CONFIG_SYS_RAMBOOT
249 #undef CONFIG_SYS_RAMBOOT
252 #define CONFIG_FLASH_CFI_DRIVER
253 #define CONFIG_SYS_FLASH_CFI
254 #define CONFIG_SYS_FLASH_EMPTY_INFO
255 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
257 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
259 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
260 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
261 #ifdef CONFIG_PHYS_64BIT
262 #define PIXIS_BASE_PHYS 0xfffdf0000ull
264 #define PIXIS_BASE_PHYS PIXIS_BASE
267 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
268 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
270 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
271 #define PIXIS_VER 0x1 /* Board version at offset 1 */
272 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
273 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
274 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
275 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
276 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
277 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
278 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
279 #define PIXIS_VCTL 0x10 /* VELA Control Register */
280 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
281 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
282 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
283 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
284 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
285 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
286 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
287 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
288 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
289 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
290 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
291 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
292 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
293 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
294 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
295 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
296 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
297 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
298 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
299 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
300 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
301 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
302 #define PIXIS_LED 0x25 /* LED Register */
304 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
306 /* old pixis referenced names */
307 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
308 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
309 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
311 #define CONFIG_SYS_INIT_RAM_LOCK 1
312 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
313 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
315 #define CONFIG_SYS_GBL_DATA_OFFSET \
316 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
319 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
320 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
322 #ifndef CONFIG_NAND_SPL
323 #define CONFIG_SYS_NAND_BASE 0xffa00000
324 #ifdef CONFIG_PHYS_64BIT
325 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
327 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
330 #define CONFIG_SYS_NAND_BASE 0xfff00000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
334 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
337 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
338 CONFIG_SYS_NAND_BASE + 0x40000, \
339 CONFIG_SYS_NAND_BASE + 0x80000, \
340 CONFIG_SYS_NAND_BASE + 0xC0000}
341 #define CONFIG_SYS_MAX_NAND_DEVICE 4
342 #define CONFIG_MTD_NAND_VERIFY_WRITE
343 #define CONFIG_CMD_NAND 1
344 #define CONFIG_NAND_FSL_ELBC 1
345 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
347 /* NAND boot: 4K NAND loader config */
348 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
349 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
350 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
351 #define CONFIG_SYS_NAND_U_BOOT_START \
352 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
353 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
354 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
355 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
357 /* NAND flash config */
358 #define CONFIG_NAND_BR_PRELIM \
359 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
360 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
361 | BR_PS_8 /* Port Size = 8 bit */ \
362 | BR_MS_FCM /* MSEL = FCM */ \
364 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
365 | OR_FCM_PGS /* Large Page*/ \
373 #ifdef CONFIG_RAMBOOT_NAND
374 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
375 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
376 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
377 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
379 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
380 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
381 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
382 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
385 #define CONFIG_SYS_BR4_PRELIM \
386 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
387 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
388 | BR_PS_8 /* Port Size = 8 bit */ \
389 | BR_MS_FCM /* MSEL = FCM */ \
391 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
392 #define CONFIG_SYS_BR5_PRELIM \
393 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
394 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
395 | BR_PS_8 /* Port Size = 8 bit */ \
396 | BR_MS_FCM /* MSEL = FCM */ \
398 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
400 #define CONFIG_SYS_BR6_PRELIM \
401 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
402 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
403 | BR_PS_8 /* Port Size = 8 bit */ \
404 | BR_MS_FCM /* MSEL = FCM */ \
406 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
408 /* Serial Port - controlled on board with jumper J8
412 #define CONFIG_CONS_INDEX 1
413 #define CONFIG_SYS_NS16550
414 #define CONFIG_SYS_NS16550_SERIAL
415 #define CONFIG_SYS_NS16550_REG_SIZE 1
416 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
417 #ifdef CONFIG_NAND_SPL
418 #define CONFIG_NS16550_MIN_FUNCTIONS
421 #define CONFIG_SYS_BAUDRATE_TABLE \
422 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
424 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
425 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
427 /* Use the HUSH parser */
428 #define CONFIG_SYS_HUSH_PARSER
429 #ifdef CONFIG_SYS_HUSH_PARSER
430 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
434 * Pass open firmware flat tree
436 #define CONFIG_OF_LIBFDT 1
437 #define CONFIG_OF_BOARD_SETUP 1
438 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
443 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
444 #define CONFIG_HARD_I2C /* I2C with hardware support */
445 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
446 #define CONFIG_I2C_MULTI_BUS
447 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
448 #define CONFIG_SYS_I2C_SLAVE 0x7F
449 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
450 #define CONFIG_SYS_I2C_OFFSET 0x3000
451 #define CONFIG_SYS_I2C2_OFFSET 0x3100
456 #define CONFIG_ID_EEPROM
457 #ifdef CONFIG_ID_EEPROM
458 #define CONFIG_SYS_I2C_EEPROM_NXID
460 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
461 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
462 #define CONFIG_SYS_EEPROM_BUS_NUM 1
466 * Memory space is mapped 1-1, but I/O space must start from 0.
469 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
472 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
474 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
475 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
477 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
478 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
479 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
480 #ifdef CONFIG_PHYS_64BIT
481 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
483 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
485 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
487 /* controller 1, Slot 1, tgtid 1, Base address a000 */
488 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
489 #ifdef CONFIG_PHYS_64BIT
490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
493 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
494 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
496 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
497 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
498 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
499 #ifdef CONFIG_PHYS_64BIT
500 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
502 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
504 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
506 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
507 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
508 #ifdef CONFIG_PHYS_64BIT
509 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
510 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
512 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
513 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
515 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
516 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
517 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
518 #ifdef CONFIG_PHYS_64BIT
519 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
521 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
523 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
525 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
526 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
527 #ifdef CONFIG_PHYS_64BIT
528 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
529 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
531 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
532 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
534 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
535 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
536 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
537 #ifdef CONFIG_PHYS_64BIT
538 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
540 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
542 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
544 #if defined(CONFIG_PCI)
546 #define CONFIG_NET_MULTI
547 #define CONFIG_PCI_PNP /* do pci plug-and-play */
549 /*PCIE video card used*/
550 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
552 /*PCI video card used*/
553 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
558 #if defined(CONFIG_VIDEO)
559 #define CONFIG_BIOSEMU
560 #define CONFIG_CFB_CONSOLE
561 #define CONFIG_VIDEO_SW_CURSOR
562 #define CONFIG_VGA_AS_SINGLE_DEVICE
563 #define CONFIG_ATI_RADEON_FB
564 #define CONFIG_VIDEO_LOGO
565 /*#define CONFIG_CONSOLE_CURSOR*/
566 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
569 #undef CONFIG_EEPRO100
571 #undef CONFIG_RTL8139
573 #ifndef CONFIG_PCI_PNP
574 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
575 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
576 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
579 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
581 #endif /* CONFIG_PCI */
584 #define CONFIG_LIBATA
585 #define CONFIG_FSL_SATA
587 #define CONFIG_SYS_SATA_MAX_DEVICE 2
589 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
590 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
592 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
593 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
595 #ifdef CONFIG_FSL_SATA
597 #define CONFIG_CMD_SATA
598 #define CONFIG_DOS_PARTITION
599 #define CONFIG_CMD_EXT2
602 #if defined(CONFIG_TSEC_ENET)
604 #ifndef CONFIG_NET_MULTI
605 #define CONFIG_NET_MULTI 1
608 #define CONFIG_MII 1 /* MII PHY management */
609 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
610 #define CONFIG_TSEC1 1
611 #define CONFIG_TSEC1_NAME "eTSEC1"
612 #define CONFIG_TSEC3 1
613 #define CONFIG_TSEC3_NAME "eTSEC3"
615 #define CONFIG_FSL_SGMII_RISER 1
616 #define SGMII_RISER_PHY_OFFSET 0x1c
618 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
619 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
621 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
622 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
624 #define TSEC1_PHYIDX 0
625 #define TSEC3_PHYIDX 0
627 #define CONFIG_ETHPRIME "eTSEC1"
629 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
631 #endif /* CONFIG_TSEC_ENET */
637 #if defined(CONFIG_SYS_RAMBOOT)
638 #if defined(CONFIG_RAMBOOT_NAND)
639 #define CONFIG_ENV_IS_IN_NAND 1
640 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
641 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
642 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
643 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
644 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
645 #define CONFIG_ENV_SIZE 0x2000
648 #define CONFIG_ENV_IS_IN_FLASH 1
649 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
650 #define CONFIG_ENV_ADDR 0xfff80000
652 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
654 #define CONFIG_ENV_SIZE 0x2000
655 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
658 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
659 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
662 * Command line configuration.
664 #include <config_cmd_default.h>
666 #define CONFIG_CMD_IRQ
667 #define CONFIG_CMD_PING
668 #define CONFIG_CMD_I2C
669 #define CONFIG_CMD_MII
670 #define CONFIG_CMD_ELF
671 #define CONFIG_CMD_IRQ
672 #define CONFIG_CMD_SETEXPR
673 #define CONFIG_CMD_REGINFO
675 #if defined(CONFIG_PCI)
676 #define CONFIG_CMD_PCI
677 #define CONFIG_CMD_NET
680 #undef CONFIG_WATCHDOG /* watchdog disabled */
685 #define CONFIG_FSL_ESDHC
686 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
687 #define CONFIG_CMD_MMC
688 #define CONFIG_GENERIC_MMC
689 #define CONFIG_CMD_EXT2
690 #define CONFIG_CMD_FAT
691 #define CONFIG_DOS_PARTITION
695 * Miscellaneous configurable options
697 #define CONFIG_SYS_LONGHELP /* undef to save memory */
698 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
699 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
700 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
701 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
702 #if defined(CONFIG_CMD_KGDB)
703 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
705 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
707 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
708 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
709 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
710 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
711 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
714 * For booting Linux, the board info and command line data
715 * have to be in the first 16 MB of memory, since this is
716 * the maximum mapped by the Linux kernel during initialization.
718 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
720 #if defined(CONFIG_CMD_KGDB)
721 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
722 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
726 * Environment Configuration
729 /* The mac addresses for all ethernet interface */
730 #if defined(CONFIG_TSEC_ENET)
731 #define CONFIG_HAS_ETH0
732 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
733 #define CONFIG_HAS_ETH1
734 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
735 #define CONFIG_HAS_ETH2
736 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
737 #define CONFIG_HAS_ETH3
738 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
741 #define CONFIG_IPADDR 192.168.1.254
743 #define CONFIG_HOSTNAME unknown
744 #define CONFIG_ROOTPATH /opt/nfsroot
745 #define CONFIG_BOOTFILE uImage
746 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
748 #define CONFIG_SERVERIP 192.168.1.1
749 #define CONFIG_GATEWAYIP 192.168.1.1
750 #define CONFIG_NETMASK 255.255.255.0
752 /* default location for tftp and bootm */
753 #define CONFIG_LOADADDR 1000000
755 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
756 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
758 #define CONFIG_BAUDRATE 115200
760 #define CONFIG_EXTRA_ENV_SETTINGS \
762 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
763 "tftpflash=tftpboot $loadaddr $uboot; " \
764 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
765 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
766 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
767 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
768 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
769 "consoledev=ttyS0\0" \
770 "ramdiskaddr=2000000\0" \
771 "ramdiskfile=8536ds/ramdisk.uboot\0" \
773 "fdtfile=8536ds/mpc8536ds.dtb\0" \
775 "usb_phy_type=ulpi\0"
777 #define CONFIG_HDBOOT \
778 "setenv bootargs root=/dev/$bdev rw " \
779 "console=$consoledev,$baudrate $othbootargs;" \
780 "tftp $loadaddr $bootfile;" \
781 "tftp $fdtaddr $fdtfile;" \
782 "bootm $loadaddr - $fdtaddr"
784 #define CONFIG_NFSBOOTCOMMAND \
785 "setenv bootargs root=/dev/nfs rw " \
786 "nfsroot=$serverip:$rootpath " \
787 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
788 "console=$consoledev,$baudrate $othbootargs;" \
789 "tftp $loadaddr $bootfile;" \
790 "tftp $fdtaddr $fdtfile;" \
791 "bootm $loadaddr - $fdtaddr"
793 #define CONFIG_RAMBOOTCOMMAND \
794 "setenv bootargs root=/dev/ram rw " \
795 "console=$consoledev,$baudrate $othbootargs;" \
796 "tftp $ramdiskaddr $ramdiskfile;" \
797 "tftp $loadaddr $bootfile;" \
798 "tftp $fdtaddr $fdtfile;" \
799 "bootm $loadaddr $ramdiskaddr $fdtaddr"
801 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
803 #endif /* __CONFIG_H */