2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8536ds board configuration file
14 #include "../board/freescale/common/ics307_clk.h"
17 #define CONFIG_RAMBOOT_SDCARD 1
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
21 #ifdef CONFIG_SPIFLASH
22 #define CONFIG_RAMBOOT_SPIFLASH 1
23 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
26 #ifndef CONFIG_RESET_VECTOR_ADDRESS
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
30 #ifndef CONFIG_SYS_MONITOR_BASE
31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
34 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
35 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
36 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
37 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
44 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
47 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
48 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
51 * These can be toggled for performance analysis, otherwise use default.
53 #define CONFIG_L2_CACHE /* toggle L2 cache */
54 #define CONFIG_BTB /* toggle branch predition */
56 #define CONFIG_ENABLE_36BIT_PHYS 1
58 #ifdef CONFIG_PHYS_64BIT
59 #define CONFIG_ADDR_MAP 1
60 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
63 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
64 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
67 * Config the L2 Cache as L2 SRAM
69 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
70 #ifdef CONFIG_PHYS_64BIT
71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
73 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
75 #define CONFIG_SYS_L2_SIZE (512 << 10)
76 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
78 #define CONFIG_SYS_CCSRBAR 0xffe00000
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
81 #if defined(CONFIG_NAND_SPL)
82 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
86 #define CONFIG_VERY_BIG_RAM
87 #undef CONFIG_FSL_DDR_INTERACTIVE
88 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
89 #define CONFIG_DDR_SPD
91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
92 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
98 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
100 /* I2C addresses of SPD EEPROMs */
101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
102 #define CONFIG_SYS_SPD_BUS_NUM 1
104 /* These are used when DDR doesn't use SPD. */
105 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
106 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
107 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
108 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
109 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
110 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
111 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
112 #define CONFIG_SYS_DDR_MODE_1 0x00480432
113 #define CONFIG_SYS_DDR_MODE_2 0x00000000
114 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
115 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
116 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
117 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
118 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
119 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
120 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
122 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
123 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
124 #define CONFIG_SYS_DDR_SBE 0x00010000
126 /* Make sure required options are set */
127 #ifndef CONFIG_SPD_EEPROM
128 #error ("CONFIG_SPD_EEPROM is required")
131 #undef CONFIG_CLOCKS_IN_MHZ
134 * Memory map -- xxx -this is wrong, needs updating
136 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
137 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
138 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
139 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
141 * Localbus cacheable (TBD)
142 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
144 * Localbus non-cacheable
145 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
146 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
147 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
148 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
149 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
150 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
154 * Local Bus Definitions
156 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
157 #ifdef CONFIG_PHYS_64BIT
158 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
160 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
163 #define CONFIG_FLASH_BR_PRELIM \
164 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
165 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
167 #define CONFIG_SYS_BR1_PRELIM \
168 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
170 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
172 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
173 CONFIG_SYS_FLASH_BASE_PHYS }
174 #define CONFIG_SYS_FLASH_QUIET_TEST
175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
177 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
178 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
179 #undef CONFIG_SYS_FLASH_CHECKSUM
180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
183 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
184 #define CONFIG_SYS_RAMBOOT
185 #define CONFIG_SYS_EXTRA_ENV_RELOC
187 #undef CONFIG_SYS_RAMBOOT
190 #define CONFIG_FLASH_CFI_DRIVER
191 #define CONFIG_SYS_FLASH_CFI
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
195 #define CONFIG_HWCONFIG /* enable hwconfig */
196 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
197 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
198 #ifdef CONFIG_PHYS_64BIT
199 #define PIXIS_BASE_PHYS 0xfffdf0000ull
201 #define PIXIS_BASE_PHYS PIXIS_BASE
204 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
205 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
207 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
208 #define PIXIS_VER 0x1 /* Board version at offset 1 */
209 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
210 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
211 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
212 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
213 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
214 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
215 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
216 #define PIXIS_VCTL 0x10 /* VELA Control Register */
217 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
218 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
219 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
220 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
221 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
222 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
223 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
224 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
225 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
226 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
227 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
228 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
229 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
230 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
231 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
232 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
233 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
234 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
235 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
236 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
237 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
238 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
239 #define PIXIS_LED 0x25 /* LED Register */
241 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
243 /* old pixis referenced names */
244 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
245 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
246 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
248 #define CONFIG_SYS_INIT_RAM_LOCK 1
249 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
250 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
252 #define CONFIG_SYS_GBL_DATA_OFFSET \
253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
254 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
256 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
257 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
259 #ifndef CONFIG_NAND_SPL
260 #define CONFIG_SYS_NAND_BASE 0xffa00000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
264 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
267 #define CONFIG_SYS_NAND_BASE 0xfff00000
268 #ifdef CONFIG_PHYS_64BIT
269 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
271 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
274 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
275 CONFIG_SYS_NAND_BASE + 0x40000, \
276 CONFIG_SYS_NAND_BASE + 0x80000, \
277 CONFIG_SYS_NAND_BASE + 0xC0000}
278 #define CONFIG_SYS_MAX_NAND_DEVICE 4
279 #define CONFIG_NAND_FSL_ELBC 1
280 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
282 /* NAND boot: 4K NAND loader config */
283 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
284 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
285 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
286 #define CONFIG_SYS_NAND_U_BOOT_START \
287 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
288 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
289 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
290 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
292 /* NAND flash config */
293 #define CONFIG_SYS_NAND_BR_PRELIM \
294 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
295 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
296 | BR_PS_8 /* Port Size = 8 bit */ \
297 | BR_MS_FCM /* MSEL = FCM */ \
299 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
300 | OR_FCM_PGS /* Large Page*/ \
308 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
309 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
310 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
311 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
313 #define CONFIG_SYS_BR4_PRELIM \
314 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
315 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
316 | BR_PS_8 /* Port Size = 8 bit */ \
317 | BR_MS_FCM /* MSEL = FCM */ \
319 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
320 #define CONFIG_SYS_BR5_PRELIM \
321 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
322 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
323 | BR_PS_8 /* Port Size = 8 bit */ \
324 | BR_MS_FCM /* MSEL = FCM */ \
326 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
328 #define CONFIG_SYS_BR6_PRELIM \
329 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
330 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
331 | BR_PS_8 /* Port Size = 8 bit */ \
332 | BR_MS_FCM /* MSEL = FCM */ \
334 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
336 /* Serial Port - controlled on board with jumper J8
340 #define CONFIG_SYS_NS16550_SERIAL
341 #define CONFIG_SYS_NS16550_REG_SIZE 1
342 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
343 #ifdef CONFIG_NAND_SPL
344 #define CONFIG_NS16550_MIN_FUNCTIONS
347 #define CONFIG_SYS_BAUDRATE_TABLE \
348 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
356 #define CONFIG_SYS_I2C
357 #define CONFIG_SYS_I2C_FSL
358 #define CONFIG_SYS_FSL_I2C_SPEED 400000
359 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
360 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
361 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
362 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
363 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
364 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
369 #define CONFIG_ID_EEPROM
370 #ifdef CONFIG_ID_EEPROM
371 #define CONFIG_SYS_I2C_EEPROM_NXID
373 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
374 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
375 #define CONFIG_SYS_EEPROM_BUS_NUM 1
378 * eSPI - Enhanced SPI
380 #define CONFIG_HARD_SPI
382 #if defined(CONFIG_SPI_FLASH)
383 #define CONFIG_SF_DEFAULT_SPEED 10000000
384 #define CONFIG_SF_DEFAULT_MODE 0
389 * Memory space is mapped 1-1, but I/O space must start from 0.
392 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
393 #ifdef CONFIG_PHYS_64BIT
394 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
395 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
397 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
398 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
400 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
401 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
402 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
403 #ifdef CONFIG_PHYS_64BIT
404 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
406 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
408 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
410 /* controller 1, Slot 1, tgtid 1, Base address a000 */
411 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
412 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
415 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
417 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
418 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
420 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
421 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
422 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
426 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
428 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
430 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
431 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
432 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
433 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
435 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
437 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
438 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
440 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
441 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
442 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
443 #ifdef CONFIG_PHYS_64BIT
444 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
446 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
448 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
450 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
451 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
452 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
453 #ifdef CONFIG_PHYS_64BIT
454 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
455 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
457 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
458 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
460 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
461 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
462 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
463 #ifdef CONFIG_PHYS_64BIT
464 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
466 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
468 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
470 #if defined(CONFIG_PCI)
471 /*PCIE video card used*/
472 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
474 /*PCI video card used*/
475 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
479 #if defined(CONFIG_VIDEO)
480 #define CONFIG_BIOSEMU
481 #define CONFIG_ATI_RADEON_FB
482 #define CONFIG_VIDEO_LOGO
483 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
486 #undef CONFIG_EEPRO100
489 #ifndef CONFIG_PCI_PNP
490 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
491 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
492 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
495 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
497 #endif /* CONFIG_PCI */
500 #define CONFIG_SYS_SATA_MAX_DEVICE 2
502 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
503 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
505 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
506 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
508 #ifdef CONFIG_FSL_SATA
512 #if defined(CONFIG_TSEC_ENET)
514 #define CONFIG_MII 1 /* MII PHY management */
515 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
516 #define CONFIG_TSEC1 1
517 #define CONFIG_TSEC1_NAME "eTSEC1"
518 #define CONFIG_TSEC3 1
519 #define CONFIG_TSEC3_NAME "eTSEC3"
521 #define CONFIG_FSL_SGMII_RISER 1
522 #define SGMII_RISER_PHY_OFFSET 0x1c
524 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
525 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
527 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
528 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
530 #define TSEC1_PHYIDX 0
531 #define TSEC3_PHYIDX 0
533 #define CONFIG_ETHPRIME "eTSEC1"
535 #endif /* CONFIG_TSEC_ENET */
541 #if defined(CONFIG_SYS_RAMBOOT)
542 #if defined(CONFIG_RAMBOOT_SPIFLASH)
543 #define CONFIG_ENV_SPI_BUS 0
544 #define CONFIG_ENV_SPI_CS 0
545 #define CONFIG_ENV_SPI_MAX_HZ 10000000
546 #define CONFIG_ENV_SPI_MODE 0
547 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
548 #define CONFIG_ENV_OFFSET 0xF0000
549 #define CONFIG_ENV_SECT_SIZE 0x10000
550 #elif defined(CONFIG_RAMBOOT_SDCARD)
551 #define CONFIG_FSL_FIXED_MMC_LOCATION
552 #define CONFIG_ENV_SIZE 0x2000
553 #define CONFIG_SYS_MMC_ENV_DEV 0
555 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
556 #define CONFIG_ENV_SIZE 0x2000
559 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
560 #define CONFIG_ENV_SIZE 0x2000
561 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
564 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
565 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
567 #undef CONFIG_WATCHDOG /* watchdog disabled */
570 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
576 #define CONFIG_HAS_FSL_MPH_USB
577 #ifdef CONFIG_HAS_FSL_MPH_USB
578 #ifdef CONFIG_USB_EHCI_HCD
579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
580 #define CONFIG_USB_EHCI_FSL
585 * Miscellaneous configurable options
587 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
590 * For booting Linux, the board info and command line data
591 * have to be in the first 64 MB of memory, since this is
592 * the maximum mapped by the Linux kernel during initialization.
594 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
595 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
597 #if defined(CONFIG_CMD_KGDB)
598 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
602 * Environment Configuration
605 /* The mac addresses for all ethernet interface */
606 #if defined(CONFIG_TSEC_ENET)
607 #define CONFIG_HAS_ETH0
608 #define CONFIG_HAS_ETH1
609 #define CONFIG_HAS_ETH2
610 #define CONFIG_HAS_ETH3
613 #define CONFIG_IPADDR 192.168.1.254
615 #define CONFIG_HOSTNAME "unknown"
616 #define CONFIG_ROOTPATH "/opt/nfsroot"
617 #define CONFIG_BOOTFILE "uImage"
618 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
620 #define CONFIG_SERVERIP 192.168.1.1
621 #define CONFIG_GATEWAYIP 192.168.1.1
622 #define CONFIG_NETMASK 255.255.255.0
624 /* default location for tftp and bootm */
625 #define CONFIG_LOADADDR 1000000
627 #define CONFIG_EXTRA_ENV_SETTINGS \
629 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot; " \
631 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
633 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
635 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
637 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
639 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
641 "consoledev=ttyS0\0" \
642 "ramdiskaddr=2000000\0" \
643 "ramdiskfile=8536ds/ramdisk.uboot\0" \
644 "fdtaddr=1e00000\0" \
645 "fdtfile=8536ds/mpc8536ds.dtb\0" \
647 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
649 #define CONFIG_HDBOOT \
650 "setenv bootargs root=/dev/$bdev rw " \
651 "console=$consoledev,$baudrate $othbootargs;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr - $fdtaddr"
656 #define CONFIG_NFSBOOTCOMMAND \
657 "setenv bootargs root=/dev/nfs rw " \
658 "nfsroot=$serverip:$rootpath " \
659 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr - $fdtaddr"
665 #define CONFIG_RAMBOOTCOMMAND \
666 "setenv bootargs root=/dev/ram rw " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $ramdiskaddr $ramdiskfile;" \
669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr $ramdiskaddr $fdtaddr"
673 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
675 #endif /* __CONFIG_H */