include/configs/MPC837XERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Kevin Lam <kevin.lam@freescale.com>
   4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  17 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
  18 #define CONFIG_MPC837XERDB      1
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  21
  22 #define CONFIG_PCI      1
  23
  24 #define CONFIG_BOARD_EARLY_INIT_F
  25 #define CONFIG_MISC_INIT_R
  26 #define CONFIG_HWCONFIG
  27
  28 /*
  29  * On-board devices
  30  */
  31 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  32 #define CONFIG_VSC7385_ENET
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #ifdef CONFIG_PCISLAVE
  38 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  39 #else
  40 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  41 #define CONFIG_PCIE
  42 #endif
  43
  44 #ifndef CONFIG_SYS_CLK_FREQ
  45 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  46 #endif
  47
  48 /*
  49  * Hardware Reset Configuration Word
  50  */
  51 #define CONFIG_SYS_HRCW_LOW (\
  52         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  53         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  54         HRCWL_SVCOD_DIV_2 |\
  55         HRCWL_CSB_TO_CLKIN_5X1 |\
  56         HRCWL_CORE_TO_CSB_2X1)
  57
  58 #ifdef CONFIG_PCISLAVE
  59 #define CONFIG_SYS_HRCW_HIGH (\
  60         HRCWH_PCI_AGENT |\
  61         HRCWH_PCI1_ARBITER_DISABLE |\
  62         HRCWH_CORE_ENABLE |\
  63         HRCWH_FROM_0XFFF00100 |\
  64         HRCWH_BOOTSEQ_DISABLE |\
  65         HRCWH_SW_WATCHDOG_DISABLE |\
  66         HRCWH_ROM_LOC_LOCAL_16BIT |\
  67         HRCWH_RL_EXT_LEGACY |\
  68         HRCWH_TSEC1M_IN_RGMII |\
  69         HRCWH_TSEC2M_IN_RGMII |\
  70         HRCWH_BIG_ENDIAN |\
  71         HRCWH_LDP_CLEAR)
  72 #else
  73 #define CONFIG_SYS_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_CORE_ENABLE |\
  77         HRCWH_FROM_0X00000100 |\
  78         HRCWH_BOOTSEQ_DISABLE |\
  79         HRCWH_SW_WATCHDOG_DISABLE |\
  80         HRCWH_ROM_LOC_LOCAL_16BIT |\
  81         HRCWH_RL_EXT_LEGACY |\
  82         HRCWH_TSEC1M_IN_RGMII |\
  83         HRCWH_TSEC2M_IN_RGMII |\
  84         HRCWH_BIG_ENDIAN |\
  85         HRCWH_LDP_CLEAR)
  86 #endif
  87
  88 /* System performance - define the value i.e. CONFIG_SYS_XXX
  89 */
  90
  91 /* Arbiter Configuration Register */
  92 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  93 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  94
  95 /* System Priority Control Regsiter */
  96 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  97
  98 /* System Clock Configuration Register */
  99 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
 100 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
 101 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
 102
 103 /*
 104  * System IO Config
 105  */
 106 #define CONFIG_SYS_SICRH                0x08200000
 107 #define CONFIG_SYS_SICRL                0x00000000
 108
 109 /*
 110  * Output Buffer Impedance
 111  */
 112 #define CONFIG_SYS_OBIR         0x30100000
 113
 114 /*
 115  * IMMR new address
 116  */
 117 #define CONFIG_SYS_IMMR         0xE0000000
 118
 119 /*
 120  * Device configurations
 121  */
 122
 123 /* Vitesse 7385 */
 124
 125 #ifdef CONFIG_VSC7385_ENET
 126
 127 #define CONFIG_TSEC2
 128
 129 /* The flash address and size of the VSC7385 firmware image */
 130 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 131 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 132
 133 #endif
 134
 135 /*
 136  * DDR Setup
 137  */
 138 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 139 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 140 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 141 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 142 #define CONFIG_SYS_83XX_DDR_USES_CS0
 143
 144 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 145
 146 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 147 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 148
 149 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 150
 151 /*
 152  * Manually set up DDR parameters
 153  */
 154 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 155 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 156 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 157                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 158                                         | CSCONFIG_ROW_BIT_13 \
 159                                         | CSCONFIG_COL_BIT_10)
 160
 161 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 162 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 163                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 164                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 165                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 166                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 167                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 168                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 169                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 170                                 /* 0x00260802 */ /* DDR400 */
 171 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 172                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 173                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 174                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 175                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 176                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 177                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 178                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 179                                 /* 0x3937d322 */
 180 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 181                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 182                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 183                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 184                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 185                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 186                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 187                                 /* 0x02984cc8 */
 188
 189 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 190                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 191                                 /* 0x06090100 */
 192
 193 #if defined(CONFIG_DDR_2T_TIMING)
 194 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 195                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 196                                         | SDRAM_CFG_32_BE \
 197                                         | SDRAM_CFG_2T_EN)
 198                                         /* 0x43088000 */
 199 #else
 200 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 201                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 202                                         /* 0x43000000 */
 203 #endif
 204 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 205 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 206                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 207                                         /* 0x04400442 */ /* DDR400 */
 208 #define CONFIG_SYS_DDR_MODE2            0x00000000
 209
 210 /*
 211  * Memory test
 212  */
 213 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 214 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 215 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 216
 217 /*
 218  * The reserved memory
 219  */
 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 221
 222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 223 #define CONFIG_SYS_RAMBOOT
 224 #else
 225 #undef  CONFIG_SYS_RAMBOOT
 226 #endif
 227
 228 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 229 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 230
 231 /*
 232  * Initial RAM Base Address Setup
 233  */
 234 #define CONFIG_SYS_INIT_RAM_LOCK        1
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 237 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 238                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 239
 240 /*
 241  * Local Bus Configuration & Clock Setup
 242  */
 243 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 244 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 245 #define CONFIG_SYS_LBC_LBCR             0x00000000
 246 #define CONFIG_FSL_ELBC         1
 247
 248 /*
 249  * FLASH on the Local Bus
 250  */
 251 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 252 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 253 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 254 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 255
 256 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 257 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 258 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
 259
 260                                         /* Window base at flash base */
 261 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 262 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 263
 264 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 265                                 | BR_PS_16      /* 16 bit port */ \
 266                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 267                                 | BR_V)         /* valid */
 268 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 269                                 | OR_GPCM_XACS \
 270                                 | OR_GPCM_SCY_9 \
 271                                 | OR_GPCM_EHTR_SET \
 272                                 | OR_GPCM_EAD)
 273                                 /* 0xFF800191 */
 274
 275 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 276 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 277
 278 #undef  CONFIG_SYS_FLASH_CHECKSUM
 279 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 280 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 281
 282 /*
 283  * NAND Flash on the Local Bus
 284  */
 285 #define CONFIG_SYS_NAND_BASE    0xE0600000
 286 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 287                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 288                                 | BR_PS_8               /* 8 bit port */ \
 289                                 | BR_MS_FCM             /* MSEL = FCM */ \
 290                                 | BR_V)                 /* valid */
 291 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 292                                 | OR_FCM_CSCT \
 293                                 | OR_FCM_CST \
 294                                 | OR_FCM_CHT \
 295                                 | OR_FCM_SCY_1 \
 296                                 | OR_FCM_TRLX \
 297                                 | OR_FCM_EHTR)
 298 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 299 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 300
 301 /* Vitesse 7385 */
 302
 303 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 304
 305 #ifdef CONFIG_VSC7385_ENET
 306
 307 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 308                                         | BR_PS_8 \
 309                                         | BR_MS_GPCM \
 310                                         | BR_V)
 311                                         /* 0xF0000801 */
 312 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 313                                         | OR_GPCM_CSNT \
 314                                         | OR_GPCM_XACS \
 315                                         | OR_GPCM_SCY_15 \
 316                                         | OR_GPCM_SETA \
 317                                         | OR_GPCM_TRLX_SET \
 318                                         | OR_GPCM_EHTR_SET \
 319                                         | OR_GPCM_EAD)
 320                                         /* 0xfffe09ff */
 321
 322                                         /* Access Base */
 323 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 324 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 325
 326 #endif
 327
 328 /*
 329  * Serial Port
 330  */
 331 #define CONFIG_CONS_INDEX       1
 332 #define CONFIG_SYS_NS16550
 333 #define CONFIG_SYS_NS16550_SERIAL
 334 #define CONFIG_SYS_NS16550_REG_SIZE     1
 335 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 336
 337 #define CONFIG_SYS_BAUDRATE_TABLE \
 338                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 339
 340 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 341 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 342
 343 /* SERDES */
 344 #define CONFIG_FSL_SERDES
 345 #define CONFIG_FSL_SERDES1      0xe3000
 346 #define CONFIG_FSL_SERDES2      0xe3100
 347
 348 /* Use the HUSH parser */
 349 #define CONFIG_SYS_HUSH_PARSER
 350
 351 /* Pass open firmware flat tree */
 352 #define CONFIG_OF_LIBFDT        1
 353 #define CONFIG_OF_BOARD_SETUP   1
 354 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
 355
 356 /* I2C */
 357 #define CONFIG_SYS_I2C
 358 #define CONFIG_SYS_I2C_FSL
 359 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 360 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 361 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 362 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 363
 364 /*
 365  * Config on-board RTC
 366  */
 367 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 368 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 369
 370 /*
 371  * General PCI
 372  * Addresses are mapped 1-1.
 373  */
 374 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 375 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 376 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 377 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 378 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 379 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 380 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 381 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 382 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 383
 384 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 385 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 386 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 387
 388 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 389 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 390 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 391 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 392 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 393 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 394 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 395 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 396 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 397
 398 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 399 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 400 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 401 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 402 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 403 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 404 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 405 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 406 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 407
 408 #ifdef CONFIG_PCI
 409 #define CONFIG_PCI_INDIRECT_BRIDGE
 410 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 411
 412 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 413 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 414 #endif  /* CONFIG_PCI */
 415
 416 /*
 417  * TSEC
 418  */
 419 #ifdef CONFIG_TSEC_ENET
 420
 421 #define CONFIG_GMII                     /* MII PHY management */
 422
 423 #define CONFIG_TSEC1
 424
 425 #ifdef CONFIG_TSEC1
 426 #define CONFIG_HAS_ETH0
 427 #define CONFIG_TSEC1_NAME               "TSEC0"
 428 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 429 #define TSEC1_PHY_ADDR                  2
 430 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 431 #define TSEC1_PHYIDX                    0
 432 #endif
 433
 434 #ifdef CONFIG_TSEC2
 435 #define CONFIG_HAS_ETH1
 436 #define CONFIG_TSEC2_NAME               "TSEC1"
 437 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 438 #define TSEC2_PHY_ADDR                  0x1c
 439 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 440 #define TSEC2_PHYIDX                    0
 441 #endif
 442
 443 /* Options are: TSEC[0-1] */
 444 #define CONFIG_ETHPRIME                 "TSEC0"
 445
 446 #endif
 447
 448 /*
 449  * SATA
 450  */
 451 #define CONFIG_LIBATA
 452 #define CONFIG_FSL_SATA
 453
 454 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 455 #define CONFIG_SATA1
 456 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 457 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 458 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 459 #define CONFIG_SATA2
 460 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 461 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 462 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 463
 464 #ifdef CONFIG_FSL_SATA
 465 #define CONFIG_LBA48
 466 #define CONFIG_CMD_SATA
 467 #define CONFIG_DOS_PARTITION
 468 #define CONFIG_CMD_EXT2
 469 #endif
 470
 471 /*
 472  * Environment
 473  */
 474 #ifndef CONFIG_SYS_RAMBOOT
 475         #define CONFIG_ENV_IS_IN_FLASH  1
 476         #define CONFIG_ENV_ADDR         \
 477                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 478         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 479         #define CONFIG_ENV_SIZE         0x4000
 480 #else
 481         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 482         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 483         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 484         #define CONFIG_ENV_SIZE         0x2000
 485 #endif
 486
 487 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 488 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 489
 490 /*
 491  * BOOTP options
 492  */
 493 #define CONFIG_BOOTP_BOOTFILESIZE
 494 #define CONFIG_BOOTP_BOOTPATH
 495 #define CONFIG_BOOTP_GATEWAY
 496 #define CONFIG_BOOTP_HOSTNAME
 497
 498
 499 /*
 500  * Command line configuration.
 501  */
 502 #include <config_cmd_default.h>
 503
 504 #define CONFIG_CMD_PING
 505 #define CONFIG_CMD_I2C
 506 #define CONFIG_CMD_MII
 507 #define CONFIG_CMD_DATE
 508
 509 #if defined(CONFIG_PCI)
 510 #define CONFIG_CMD_PCI
 511 #endif
 512
 513 #if defined(CONFIG_SYS_RAMBOOT)
 514 #undef CONFIG_CMD_SAVEENV
 515 #undef CONFIG_CMD_LOADS
 516 #endif
 517
 518 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 519 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 520
 521 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 522
 523 #define CONFIG_MMC     1
 524
 525 #ifdef CONFIG_MMC
 526 #define CONFIG_FSL_ESDHC
 527 #define CONFIG_FSL_ESDHC_PIN_MUX
 528 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 529 #define CONFIG_CMD_MMC
 530 #define CONFIG_GENERIC_MMC
 531 #define CONFIG_CMD_EXT2
 532 #define CONFIG_CMD_FAT
 533 #define CONFIG_DOS_PARTITION
 534 #endif
 535
 536 /*
 537  * Miscellaneous configurable options
 538  */
 539 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 540 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 541 #define CONFIG_SYS_PROMPT       "=> "   /* Monitor Command Prompt */
 542
 543 #if defined(CONFIG_CMD_KGDB)
 544         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 545 #else
 546         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 547 #endif
 548
 549                                 /* Print Buffer Size */
 550 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 551 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 552                                 /* Boot Argument Buffer Size */
 553 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 554 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 555
 556 /*
 557  * For booting Linux, the board info and command line data
 558  * have to be in the first 256 MB of memory, since this is
 559  * the maximum mapped by the Linux kernel during initialization.
 560  */
 561 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 562
 563 /*
 564  * Core HID Setup
 565  */
 566 #define CONFIG_SYS_HID0_INIT    0x000000000
 567 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 568                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 569 #define CONFIG_SYS_HID2         HID2_HBE
 570
 571 /*
 572  * MMU Setup
 573  */
 574
 575 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 576
 577 /* DDR: cache cacheable */
 578 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 579 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 580
 581 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 582                                 | BATL_PP_RW \
 583                                 | BATL_MEMCOHERENCE)
 584 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 585                                 | BATU_BL_256M \
 586                                 | BATU_VS \
 587                                 | BATU_VP)
 588 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 589 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 590
 591 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 592                                 | BATL_PP_RW \
 593                                 | BATL_MEMCOHERENCE)
 594 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 595                                 | BATU_BL_256M \
 596                                 | BATU_VS \
 597                                 | BATU_VP)
 598 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 599 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 600
 601 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 602 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 603                                 | BATL_PP_RW \
 604                                 | BATL_CACHEINHIBIT \
 605                                 | BATL_GUARDEDSTORAGE)
 606 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 607                                 | BATU_BL_8M \
 608                                 | BATU_VS \
 609                                 | BATU_VP)
 610 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 611 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 612
 613 /* L2 Switch: cache-inhibit and guarded */
 614 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 615                                 | BATL_PP_RW \
 616                                 | BATL_CACHEINHIBIT \
 617                                 | BATL_GUARDEDSTORAGE)
 618 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 619                                 | BATU_BL_128K \
 620                                 | BATU_VS \
 621                                 | BATU_VP)
 622 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 623 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 624
 625 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 626 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 627                                 | BATL_PP_RW \
 628                                 | BATL_MEMCOHERENCE)
 629 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 630                                 | BATU_BL_32M \
 631                                 | BATU_VS \
 632                                 | BATU_VP)
 633 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 634                                 | BATL_PP_RW \
 635                                 | BATL_CACHEINHIBIT \
 636                                 | BATL_GUARDEDSTORAGE)
 637 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 638
 639 /* Stack in dcache: cacheable, no memory coherence */
 640 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 641 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 642                                 | BATU_BL_128K \
 643                                 | BATU_VS \
 644                                 | BATU_VP)
 645 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 646 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 647
 648 #ifdef CONFIG_PCI
 649 /* PCI MEM space: cacheable */
 650 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 651                                 | BATL_PP_RW \
 652                                 | BATL_MEMCOHERENCE)
 653 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 654                                 | BATU_BL_256M \
 655                                 | BATU_VS \
 656                                 | BATU_VP)
 657 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 658 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 659 /* PCI MMIO space: cache-inhibit and guarded */
 660 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 661                                 | BATL_PP_RW \
 662                                 | BATL_CACHEINHIBIT \
 663                                 | BATL_GUARDEDSTORAGE)
 664 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 665                                 | BATU_BL_256M \
 666                                 | BATU_VS \
 667                                 | BATU_VP)
 668 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 669 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 670 #else
 671 #define CONFIG_SYS_IBAT6L       (0)
 672 #define CONFIG_SYS_IBAT6U       (0)
 673 #define CONFIG_SYS_IBAT7L       (0)
 674 #define CONFIG_SYS_IBAT7U       (0)
 675 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 676 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 677 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 678 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 679 #endif
 680
 681 #if defined(CONFIG_CMD_KGDB)
 682 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 683 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 684 #endif
 685
 686 /*
 687  * Environment Configuration
 688  */
 689 #define CONFIG_ENV_OVERWRITE
 690
 691 #define CONFIG_HAS_FSL_DR_USB
 692
 693 #define CONFIG_NETDEV           "eth1"
 694
 695 #define CONFIG_HOSTNAME         mpc837x_rdb
 696 #define CONFIG_ROOTPATH         "/nfsroot"
 697 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 698 #define CONFIG_BOOTFILE         "uImage"
 699                                 /* U-Boot image on TFTP server */
 700 #define CONFIG_UBOOTPATH        "u-boot.bin"
 701 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 702
 703                                 /* default location for tftp and bootm */
 704 #define CONFIG_LOADADDR         800000
 705 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 706 #define CONFIG_BAUDRATE         115200
 707
 708 #define CONFIG_EXTRA_ENV_SETTINGS \
 709         "netdev=" CONFIG_NETDEV "\0"                            \
 710         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 711         "tftpflash=tftp $loadaddr $uboot;"                              \
 712                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 713                         " +$filesize; " \
 714                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 715                         " +$filesize; " \
 716                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 717                         " $filesize; "  \
 718                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 719                         " +$filesize; " \
 720                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 721                         " $filesize\0"  \
 722         "fdtaddr=780000\0"                                              \
 723         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 724         "ramdiskaddr=1000000\0"                                         \
 725         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 726         "console=ttyS0\0"                                               \
 727         "setbootargs=setenv bootargs "                                  \
 728                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 729         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 730                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 731                                                         "$netdev:off "  \
 732                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 733
 734 #define CONFIG_NFSBOOTCOMMAND                                           \
 735         "setenv rootdev /dev/nfs;"                                      \
 736         "run setbootargs;"                                              \
 737         "run setipargs;"                                                \
 738         "tftp $loadaddr $bootfile;"                                     \
 739         "tftp $fdtaddr $fdtfile;"                                       \
 740         "bootm $loadaddr - $fdtaddr"
 741
 742 #define CONFIG_RAMBOOTCOMMAND                                           \
 743         "setenv rootdev /dev/ram;"                                      \
 744         "run setbootargs;"                                              \
 745         "tftp $ramdiskaddr $ramdiskfile;"                               \
 746         "tftp $loadaddr $bootfile;"                                     \
 747         "tftp $fdtaddr $fdtfile;"                                       \
 748         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 749
 750 #endif  /* __CONFIG_H */