include/configs/MPC837XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Dave Liu <daveliu@freescale.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * High Level Configuration Options
  12  */
  13 #define CONFIG_E300             1 /* E300 family */
  14
  15 /*
  16  * IP blocks clock configuration
  17  */
  18 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  19 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  20 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
  21
  22 /*
  23  * System IO Config
  24  */
  25 #define CONFIG_SYS_SICRH                0x00000000
  26 #define CONFIG_SYS_SICRL                0x00000000
  27
  28 /*
  29  * Output Buffer Impedance
  30  */
  31 #define CONFIG_SYS_OBIR         0x31100000
  32
  33 #define CONFIG_HWCONFIG
  34
  35 /*
  36  * DDR Setup
  37  */
  38 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  39 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_SDRAM_BASE
  40 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  41 #define CONFIG_SYS_83XX_DDR_USES_CS0
  42 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
  43                                         | DDRCDR_ODT \
  44                                         | DDRCDR_Q_DRN)
  45                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
  46
  47 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
  48 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
  49
  50 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
  51 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  52
  53 #if defined(CONFIG_SPD_EEPROM)
  54 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
  55 #else
  56 /*
  57  * Manually set up DDR parameters
  58  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  59  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  60  */
  61 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
  62 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  63 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  64                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
  65                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
  66                         | CSCONFIG_ROW_BIT_14 \
  67                         | CSCONFIG_COL_BIT_10)
  68                         /* 0x80010202 */
  69 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  70 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  71                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  72                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  73                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  74                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  75                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  76                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  77                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  78                                 /* 0x00620802 */
  79 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  80                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  81                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  82                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  83                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  84                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  85                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  86                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  87                                 /* 0x3935d322 */
  88 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  89                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
  90                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  91                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  92                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  93                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  94                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
  95                                 /* 0x131088c8 */
  96 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
  97                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  98                                 /* 0x03E00100 */
  99 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 100 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 101 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 102                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
 103                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 104 #define CONFIG_SYS_DDR_MODE2    0x00000000
 105 #endif
 106
 107 /*
 108  * Memory test
 109  */
 110 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 111 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 112 #define CONFIG_SYS_MEMTEST_END          0x00140000
 113
 114 /*
 115  * The reserved memory
 116  */
 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 118
 119 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 120 #define CONFIG_SYS_RAMBOOT
 121 #else
 122 #undef CONFIG_SYS_RAMBOOT
 123 #endif
 124
 125 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 126 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 127 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 128
 129 /*
 130  * Initial RAM Base Address Setup
 131  */
 132 #define CONFIG_SYS_INIT_RAM_LOCK        1
 133 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 134 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 135 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 136                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137
 138 /*
 139  * Local Bus Configuration & Clock Setup
 140  */
 141 #define CONFIG_SYS_LBC_LBCR             0x00000000
 142 #define CONFIG_FSL_ELBC         1
 143
 144 /*
 145  * FLASH on the Local Bus
 146  */
 147 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 148 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 149
 150
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 152 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 153
 154 #undef CONFIG_SYS_FLASH_CHECKSUM
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 157
 158 /*
 159  * BCSR on the Local Bus
 160  */
 161 #define CONFIG_SYS_BCSR         0xF8000000
 162                                         /* Access window base at BCSR base */
 163
 164 /*
 165  * NAND Flash on the Local Bus
 166  */
 167 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 168 #define CONFIG_NAND_FSL_ELBC    1
 169
 170 #define CONFIG_SYS_NAND_BASE    0xE0600000
 171
 172
 173 /*
 174  * Serial Port
 175  */
 176 #define CONFIG_SYS_NS16550_SERIAL
 177 #define CONFIG_SYS_NS16550_REG_SIZE     1
 178 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 179
 180 #define CONFIG_SYS_BAUDRATE_TABLE  \
 181                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 182
 183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 185
 186 /* I2C */
 187 #define CONFIG_SYS_I2C
 188 #define CONFIG_SYS_I2C_FSL
 189 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 190 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 191 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 192 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 193
 194 /*
 195  * Config on-board RTC
 196  */
 197 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 198 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 199
 200 /*
 201  * General PCI
 202  * Addresses are mapped 1-1.
 203  */
 204 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 205 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 206 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 207 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 208 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 209 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 210 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 211 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 212 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 213
 214 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 215 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 216 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 217
 218 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 219 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 220 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 221 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 222 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 223 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 224 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 225 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 226 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 227
 228 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 229 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 230 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 231 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 232 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 233 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 234 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 235 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 236 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 237
 238 #ifdef CONFIG_PCI
 239 #define CONFIG_PCI_INDIRECT_BRIDGE
 240 #ifndef __ASSEMBLY__
 241 extern int board_pci_host_broken(void);
 242 #endif
 243 #define CONFIG_PCIE
 244 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 245
 246 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 247 #define CONFIG_USB_EHCI_FSL
 248 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 249
 250 #undef CONFIG_EEPRO100
 251 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 252 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 253 #endif /* CONFIG_PCI */
 254
 255 /*
 256  * TSEC
 257  */
 258 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 259 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 260 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 261 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 262
 263 /*
 264  * TSEC ethernet configuration
 265  */
 266 #define CONFIG_TSEC1            1
 267 #define CONFIG_TSEC1_NAME       "eTSEC0"
 268 #define CONFIG_TSEC2            1
 269 #define CONFIG_TSEC2_NAME       "eTSEC1"
 270 #define TSEC1_PHY_ADDR          2
 271 #define TSEC2_PHY_ADDR          3
 272 #define TSEC1_PHY_ADDR_SGMII    8
 273 #define TSEC2_PHY_ADDR_SGMII    4
 274 #define TSEC1_PHYIDX            0
 275 #define TSEC2_PHYIDX            0
 276 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 277 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 278
 279 /* Options are: TSEC[0-1] */
 280 #define CONFIG_ETHPRIME         "eTSEC1"
 281
 282 /* SERDES */
 283 #define CONFIG_FSL_SERDES
 284 #define CONFIG_FSL_SERDES1      0xe3000
 285 #define CONFIG_FSL_SERDES2      0xe3100
 286
 287 /*
 288  * SATA
 289  */
 290 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 291 #define CONFIG_SATA1
 292 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 293 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 294 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 295 #define CONFIG_SATA2
 296 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 297 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 298 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 299
 300 #ifdef CONFIG_FSL_SATA
 301 #define CONFIG_LBA48
 302 #endif
 303
 304 /*
 305  * Environment
 306  */
 307 #ifndef CONFIG_SYS_RAMBOOT
 308         #define CONFIG_ENV_ADDR         \
 309                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 310         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 311         #define CONFIG_ENV_SIZE         0x2000
 312 #else
 313         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 314         #define CONFIG_ENV_SIZE         0x2000
 315 #endif
 316
 317 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 318 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 319
 320 /*
 321  * BOOTP options
 322  */
 323 #define CONFIG_BOOTP_BOOTFILESIZE
 324
 325 /*
 326  * Command line configuration.
 327  */
 328
 329 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 330
 331 #ifdef CONFIG_MMC
 332 #define CONFIG_FSL_ESDHC_PIN_MUX
 333 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 334 #endif
 335
 336 /*
 337  * Miscellaneous configurable options
 338  */
 339 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 340
 341 /*
 342  * For booting Linux, the board info and command line data
 343  * have to be in the first 256 MB of memory, since this is
 344  * the maximum mapped by the Linux kernel during initialization.
 345  */
 346 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 347 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 348
 349 #if defined(CONFIG_CMD_KGDB)
 350 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 351 #endif
 352
 353 /*
 354  * Environment Configuration
 355  */
 356
 357 #define CONFIG_ENV_OVERWRITE
 358
 359 #if defined(CONFIG_TSEC_ENET)
 360 #define CONFIG_HAS_ETH0
 361 #define CONFIG_HAS_ETH1
 362 #endif
 363
 364 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 365
 366 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 367         "netdev=eth0\0"                                                 \
 368         "consoledev=ttyS0\0"                                            \
 369         "ramdiskaddr=1000000\0"                                         \
 370         "ramdiskfile=ramfs.83xx\0"                                      \
 371         "fdtaddr=780000\0"                                              \
 372         "fdtfile=mpc8379_mds.dtb\0"                                     \
 373         ""
 374
 375 #define CONFIG_NFSBOOTCOMMAND                                           \
 376         "setenv bootargs root=/dev/nfs rw "                             \
 377                 "nfsroot=$serverip:$rootpath "                          \
 378                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 379                                                         "$netdev:off "  \
 380                 "console=$consoledev,$baudrate $othbootargs;"           \
 381         "tftp $loadaddr $bootfile;"                                     \
 382         "tftp $fdtaddr $fdtfile;"                                       \
 383         "bootm $loadaddr - $fdtaddr"
 384
 385 #define CONFIG_RAMBOOTCOMMAND                                           \
 386         "setenv bootargs root=/dev/ram rw "                             \
 387                 "console=$consoledev,$baudrate $othbootargs;"           \
 388         "tftp $ramdiskaddr $ramdiskfile;"                               \
 389         "tftp $loadaddr $bootfile;"                                     \
 390         "tftp $fdtaddr $fdtfile;"                                       \
 391         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 392
 393 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 394
 395 #endif  /* __CONFIG_H */