include/configs/MPC837XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Dave Liu <daveliu@freescale.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * High Level Configuration Options
  12  */
  13 #define CONFIG_E300             1 /* E300 family */
  14
  15 /* Arbiter Configuration Register */
  16 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  17 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
  18
  19 /* System Priority Control Register */
  20 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
  21
  22 /*
  23  * IP blocks clock configuration
  24  */
  25 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  26 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  27 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
  28
  29 /*
  30  * System IO Config
  31  */
  32 #define CONFIG_SYS_SICRH                0x00000000
  33 #define CONFIG_SYS_SICRL                0x00000000
  34
  35 /*
  36  * Output Buffer Impedance
  37  */
  38 #define CONFIG_SYS_OBIR         0x31100000
  39
  40 #define CONFIG_HWCONFIG
  41
  42 /*
  43  * DDR Setup
  44  */
  45 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  46 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  47 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  48 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  49 #define CONFIG_SYS_83XX_DDR_USES_CS0
  50 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
  51                                         | DDRCDR_ODT \
  52                                         | DDRCDR_Q_DRN)
  53                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
  54
  55 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
  56 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
  57
  58 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
  59 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
  60
  61 #if defined(CONFIG_SPD_EEPROM)
  62 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
  63 #else
  64 /*
  65  * Manually set up DDR parameters
  66  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
  67  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
  68  */
  69 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
  70 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
  71 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  72                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
  73                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
  74                         | CSCONFIG_ROW_BIT_14 \
  75                         | CSCONFIG_COL_BIT_10)
  76                         /* 0x80010202 */
  77 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  78 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  79                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  80                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  81                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  82                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  83                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  84                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  85                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  86                                 /* 0x00620802 */
  87 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  88                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  89                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  90                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  91                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
  92                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
  93                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  94                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  95                                 /* 0x3935d322 */
  96 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  97                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
  98                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  99                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 100                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 101                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 102                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 103                                 /* 0x131088c8 */
 104 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
 105                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 106                                 /* 0x03E00100 */
 107 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 108 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 109 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 110                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
 111                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 112 #define CONFIG_SYS_DDR_MODE2    0x00000000
 113 #endif
 114
 115 /*
 116  * Memory test
 117  */
 118 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 119 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 120 #define CONFIG_SYS_MEMTEST_END          0x00140000
 121
 122 /*
 123  * The reserved memory
 124  */
 125 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 126
 127 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 128 #define CONFIG_SYS_RAMBOOT
 129 #else
 130 #undef CONFIG_SYS_RAMBOOT
 131 #endif
 132
 133 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 134 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 135 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 136
 137 /*
 138  * Initial RAM Base Address Setup
 139  */
 140 #define CONFIG_SYS_INIT_RAM_LOCK        1
 141 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 142 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 143 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 144                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 145
 146 /*
 147  * Local Bus Configuration & Clock Setup
 148  */
 149 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 150 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 151 #define CONFIG_SYS_LBC_LBCR             0x00000000
 152 #define CONFIG_FSL_ELBC         1
 153
 154 /*
 155  * FLASH on the Local Bus
 156  */
 157 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 158 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 159
 160
 161 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 162 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 163
 164 #undef CONFIG_SYS_FLASH_CHECKSUM
 165 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 166 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 167
 168 /*
 169  * BCSR on the Local Bus
 170  */
 171 #define CONFIG_SYS_BCSR         0xF8000000
 172                                         /* Access window base at BCSR base */
 173
 174 /*
 175  * NAND Flash on the Local Bus
 176  */
 177 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 178 #define CONFIG_NAND_FSL_ELBC    1
 179
 180 #define CONFIG_SYS_NAND_BASE    0xE0600000
 181
 182
 183 /*
 184  * Serial Port
 185  */
 186 #define CONFIG_SYS_NS16550_SERIAL
 187 #define CONFIG_SYS_NS16550_REG_SIZE     1
 188 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 189
 190 #define CONFIG_SYS_BAUDRATE_TABLE  \
 191                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 192
 193 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 194 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 195
 196 /* I2C */
 197 #define CONFIG_SYS_I2C
 198 #define CONFIG_SYS_I2C_FSL
 199 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 200 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 201 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 202 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 203
 204 /*
 205  * Config on-board RTC
 206  */
 207 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 208 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 209
 210 /*
 211  * General PCI
 212  * Addresses are mapped 1-1.
 213  */
 214 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 215 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 216 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 217 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 218 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 219 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 220 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 221 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 222 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 223
 224 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 225 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 226 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 227
 228 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 229 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 230 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 231 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 232 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 233 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 234 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 235 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 236 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 237
 238 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 239 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 240 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 241 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 242 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 243 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 244 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 245 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 246 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 247
 248 #ifdef CONFIG_PCI
 249 #define CONFIG_PCI_INDIRECT_BRIDGE
 250 #ifndef __ASSEMBLY__
 251 extern int board_pci_host_broken(void);
 252 #endif
 253 #define CONFIG_PCIE
 254 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 255
 256 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 257 #define CONFIG_USB_EHCI_FSL
 258 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 259
 260 #undef CONFIG_EEPRO100
 261 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 263 #endif /* CONFIG_PCI */
 264
 265 /*
 266  * TSEC
 267  */
 268 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 269 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 270 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 271 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 272
 273 /*
 274  * TSEC ethernet configuration
 275  */
 276 #define CONFIG_TSEC1            1
 277 #define CONFIG_TSEC1_NAME       "eTSEC0"
 278 #define CONFIG_TSEC2            1
 279 #define CONFIG_TSEC2_NAME       "eTSEC1"
 280 #define TSEC1_PHY_ADDR          2
 281 #define TSEC2_PHY_ADDR          3
 282 #define TSEC1_PHY_ADDR_SGMII    8
 283 #define TSEC2_PHY_ADDR_SGMII    4
 284 #define TSEC1_PHYIDX            0
 285 #define TSEC2_PHYIDX            0
 286 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 287 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 288
 289 /* Options are: TSEC[0-1] */
 290 #define CONFIG_ETHPRIME         "eTSEC1"
 291
 292 /* SERDES */
 293 #define CONFIG_FSL_SERDES
 294 #define CONFIG_FSL_SERDES1      0xe3000
 295 #define CONFIG_FSL_SERDES2      0xe3100
 296
 297 /*
 298  * SATA
 299  */
 300 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 301 #define CONFIG_SATA1
 302 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 303 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 304 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 305 #define CONFIG_SATA2
 306 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 307 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 308 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 309
 310 #ifdef CONFIG_FSL_SATA
 311 #define CONFIG_LBA48
 312 #endif
 313
 314 /*
 315  * Environment
 316  */
 317 #ifndef CONFIG_SYS_RAMBOOT
 318         #define CONFIG_ENV_ADDR         \
 319                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 320         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 321         #define CONFIG_ENV_SIZE         0x2000
 322 #else
 323         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 324         #define CONFIG_ENV_SIZE         0x2000
 325 #endif
 326
 327 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 328 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 329
 330 /*
 331  * BOOTP options
 332  */
 333 #define CONFIG_BOOTP_BOOTFILESIZE
 334
 335 /*
 336  * Command line configuration.
 337  */
 338
 339 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 340
 341 #ifdef CONFIG_MMC
 342 #define CONFIG_FSL_ESDHC_PIN_MUX
 343 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 344 #endif
 345
 346 /*
 347  * Miscellaneous configurable options
 348  */
 349 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 350
 351 /*
 352  * For booting Linux, the board info and command line data
 353  * have to be in the first 256 MB of memory, since this is
 354  * the maximum mapped by the Linux kernel during initialization.
 355  */
 356 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 357 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 358
 359 #if defined(CONFIG_CMD_KGDB)
 360 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 361 #endif
 362
 363 /*
 364  * Environment Configuration
 365  */
 366
 367 #define CONFIG_ENV_OVERWRITE
 368
 369 #if defined(CONFIG_TSEC_ENET)
 370 #define CONFIG_HAS_ETH0
 371 #define CONFIG_HAS_ETH1
 372 #endif
 373
 374 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 375
 376 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 377         "netdev=eth0\0"                                                 \
 378         "consoledev=ttyS0\0"                                            \
 379         "ramdiskaddr=1000000\0"                                         \
 380         "ramdiskfile=ramfs.83xx\0"                                      \
 381         "fdtaddr=780000\0"                                              \
 382         "fdtfile=mpc8379_mds.dtb\0"                                     \
 383         ""
 384
 385 #define CONFIG_NFSBOOTCOMMAND                                           \
 386         "setenv bootargs root=/dev/nfs rw "                             \
 387                 "nfsroot=$serverip:$rootpath "                          \
 388                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 389                                                         "$netdev:off "  \
 390                 "console=$consoledev,$baudrate $othbootargs;"           \
 391         "tftp $loadaddr $bootfile;"                                     \
 392         "tftp $fdtaddr $fdtfile;"                                       \
 393         "bootm $loadaddr - $fdtaddr"
 394
 395 #define CONFIG_RAMBOOTCOMMAND                                           \
 396         "setenv bootargs root=/dev/ram rw "                             \
 397                 "console=$consoledev,$baudrate $othbootargs;"           \
 398         "tftp $ramdiskaddr $ramdiskfile;"                               \
 399         "tftp $loadaddr $bootfile;"                                     \
 400         "tftp $fdtaddr $fdtfile;"                                       \
 401         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 402
 403 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 404
 405 #endif  /* __CONFIG_H */