2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
21 * High Level Configuration Options
23 #define CONFIG_E300 1 /* E300 family */
24 #define CONFIG_QE 1 /* Has QE */
25 #define CONFIG_MPC83XX 1 /* MPC83XX family */
26 #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
27 #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
32 #ifdef CONFIG_CLKIN_33MHZ
33 #define CONFIG_83XX_CLKIN 33000000
34 #define CONFIG_SYS_CLK_FREQ 33000000
36 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
38 #define CONFIG_83XX_CLKIN 66000000
39 #define CONFIG_SYS_CLK_FREQ 66000000
41 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
42 #endif /* CONFIG_CLKIN_33MHZ */
45 * Hardware Reset Configuration Word
47 #define CFG_HRCW_LOW (\
48 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
49 HRCWL_DDR_TO_SCB_CLK_1X1 |\
50 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
51 HRCWL_CORE_TO_CSB_2X1 |\
54 #define CFG_HRCW_HIGH (\
56 HRCWH_PCI1_ARBITER_ENABLE |\
57 HRCWH_PCICKDRV_ENABLE |\
59 HRCWH_FROM_0X00000100 |\
60 HRCWH_BOOTSEQ_DISABLE |\
61 HRCWH_SW_WATCHDOG_DISABLE |\
62 HRCWH_ROM_LOC_LOCAL_16BIT |\
63 HRCWH_SECONDARY_DDR_DISABLE |\
70 #define CFG_SICRH 0x00000000
71 #define CFG_SICRL 0x40000000
73 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
74 #define CONFIG_BOARD_EARLY_INIT_R
79 #define CFG_IMMR 0xE0000000
84 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
85 #define CFG_SDRAM_BASE CFG_DDR_BASE
86 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
87 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
88 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
90 #define CFG_83XX_DDR_USES_CS0
92 #undef CONFIG_DDR_ECC /* support DDR ECC function */
93 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
96 * DDRCDR - DDR Control Driver Register
98 #define CFG_DDRCDR_VALUE 0x80080001
100 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
103 * Manually set up DDR parameters
105 #define CONFIG_DDR_II
106 #define CFG_DDR_SIZE 256 /* MB */
107 #define CFG_DDRCDR 0x80080001
108 #define CFG_DDR_CS0_BNDS 0x0000000f
109 #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
111 #define CFG_DDR_TIMING_0 0x00330903
112 #define CFG_DDR_TIMING_1 0x3835a322
113 #define CFG_DDR_TIMING_2 0x00104909
114 #define CFG_DDR_TIMING_3 0x00000000
115 #define CFG_DDR_CLK_CNTL 0x02000000
116 #define CFG_DDR_MODE 0x47800432
117 #define CFG_DDR_MODE2 0x8000c000
118 #define CFG_DDR_INTERVAL 0x045b0100
119 #define CFG_DDR_SDRAM_CFG 0x03000000
120 #define CFG_DDR_SDRAM_CFG2 0x00001000
125 #undef CFG_DRAM_TEST /* memory test, takes time */
126 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
127 #define CFG_MEMTEST_END 0x00100000
130 * The reserved memory
132 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
133 #define CFG_FLASH_BASE 0xFF800000 /* FLASH base address */
135 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
141 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
142 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
145 * Initial RAM Base Address Setup
147 #define CFG_INIT_RAM_LOCK 1
148 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
150 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
151 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
154 * Local Bus Configuration & Clock Setup
156 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
157 #define CFG_LBC_LBCR 0x00000000
160 * FLASH on the Local Bus
162 #define CFG_FLASH_CFI /* use the Common Flash Interface */
163 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
164 #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
165 #define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */
167 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
168 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
170 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
171 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
173 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
174 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
175 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
176 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
178 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
179 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
181 #undef CFG_FLASH_CHECKSUM
184 * NAND flash on the local bus
186 #define CFG_NAND_BASE 0x60000000
187 #define CONFIG_CMD_NAND 1
188 #define CONFIG_NAND_FSL_UPM 1
189 #define CFG_MAX_NAND_DEVICE 1
190 #define NAND_MAX_CHIPS 1
191 #define CONFIG_MTD_NAND_VERIFY_WRITE
193 #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
194 #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
196 /* Port size 8 bit, UPMA */
197 #define CFG_BR1_PRELIM (CFG_NAND_BASE | 0x00000881)
198 #define CFG_OR1_PRELIM 0xfc000001
201 * Fujitsu MB86277 (MINT) graphics controller
203 #define CFG_VIDEO_BASE 0x70000000
205 #define CFG_LBLAWBAR2_PRELIM CFG_VIDEO_BASE
206 #define CFG_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
208 /* Port size 32 bit, UPMB */
209 #define CFG_BR2_PRELIM (CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
210 #define CFG_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
215 #define CONFIG_CONS_INDEX 1
216 #undef CONFIG_SERIAL_SOFTWARE_FIFO
218 #define CFG_NS16550_SERIAL
219 #define CFG_NS16550_REG_SIZE 1
220 #define CFG_NS16550_CLK get_bus_freq(0)
222 #define CFG_BAUDRATE_TABLE \
223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
225 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
226 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
228 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
229 /* Use the HUSH parser */
230 #define CFG_HUSH_PARSER
231 #ifdef CFG_HUSH_PARSER
232 #define CFG_PROMPT_HUSH_PS2 "> "
235 /* Pass open firmware flat tree */
236 #define CONFIG_OF_LIBFDT 1
237 #define CONFIG_OF_BOARD_SETUP 1
240 #define CONFIG_HARD_I2C /* I2C with hardware support */
241 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
242 #define CONFIG_FSL_I2C
243 #define CONFIG_I2C_MULTI_BUS
244 #define CONFIG_I2C_CMD_TREE
245 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
246 #define CFG_I2C_SLAVE 0x7F
247 #define CFG_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
248 #define CFG_I2C_OFFSET 0x3000
249 #define CFG_I2C2_OFFSET 0x3100
253 * Addresses are mapped 1-1.
256 #define CONFIG_83XX_GENERIC_PCI 1
258 #define CFG_PCI1_MEM_BASE 0x80000000
259 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
260 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
261 #define CFG_PCI1_MMIO_BASE 0x90000000
262 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
263 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
264 #define CFG_PCI1_IO_BASE 0xE0300000
265 #define CFG_PCI1_IO_PHYS 0xE0300000
266 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
270 #define CONFIG_NET_MULTI
271 #define CONFIG_PCI_PNP /* do pci plug-and-play */
273 #undef CONFIG_EEPRO100
274 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
275 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
277 #endif /* CONFIG_PCI */
280 #ifndef CONFIG_NET_MULTI
281 #define CONFIG_NET_MULTI 1
285 * QE UEC ethernet configuration
287 #define CONFIG_UEC_ETH
288 #define CONFIG_ETHPRIME "FSL UEC0"
290 #define CONFIG_UEC_ETH1 /* GETH1 */
292 #ifdef CONFIG_UEC_ETH1
293 #define CFG_UEC1_UCC_NUM 0 /* UCC1 */
294 #define CFG_UEC1_RX_CLK QE_CLK_NONE
295 #define CFG_UEC1_TX_CLK QE_CLK9
296 #define CFG_UEC1_ETH_TYPE GIGA_ETH
297 #define CFG_UEC1_PHY_ADDR 2
298 #define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
301 #define CONFIG_UEC_ETH2 /* GETH2 */
303 #ifdef CONFIG_UEC_ETH2
304 #define CFG_UEC2_UCC_NUM 1 /* UCC2 */
305 #define CFG_UEC2_RX_CLK QE_CLK_NONE
306 #define CFG_UEC2_TX_CLK QE_CLK4
307 #define CFG_UEC2_ETH_TYPE GIGA_ETH
308 #define CFG_UEC2_PHY_ADDR 4
309 #define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
317 #define CFG_ENV_IS_IN_FLASH 1
318 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
319 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
320 #define CFG_ENV_SIZE 0x20000
321 #else /* CFG_RAMBOOT */
322 #define CFG_NO_FLASH 1 /* Flash is not usable now */
323 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
324 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
325 #define CFG_ENV_SIZE 0x2000
326 #endif /* CFG_RAMBOOT */
328 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
329 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
334 #define CONFIG_BOOTP_BOOTFILESIZE
335 #define CONFIG_BOOTP_BOOTPATH
336 #define CONFIG_BOOTP_GATEWAY
337 #define CONFIG_BOOTP_HOSTNAME
341 * Command line configuration.
343 #include <config_cmd_default.h>
345 #define CONFIG_CMD_PING
346 #define CONFIG_CMD_I2C
347 #define CONFIG_CMD_ASKENV
349 #if defined(CONFIG_PCI)
350 #define CONFIG_CMD_PCI
353 #if defined(CFG_RAMBOOT)
354 #undef CONFIG_CMD_ENV
355 #undef CONFIG_CMD_LOADS
358 #undef CONFIG_WATCHDOG /* watchdog disabled */
361 * Miscellaneous configurable options
363 #define CFG_LONGHELP /* undef to save memory */
364 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
365 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
367 #if defined(CONFIG_CMD_KGDB)
368 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
370 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
373 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
374 #define CFG_MAXARGS 16 /* max number of command args */
375 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
376 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
379 * For booting Linux, the board info and command line data
380 * have to be in the first 8 MB of memory, since this is
381 * the maximum mapped by the Linux kernel during initialization.
383 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
388 #define CFG_HID0_INIT 0x000000000
389 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
390 #define CFG_HID2 HID2_HBE
396 /* DDR: cache cacheable */
397 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
398 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
399 #define CFG_DBAT0L CFG_IBAT0L
400 #define CFG_DBAT0U CFG_IBAT0U
402 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
403 #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
404 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
405 #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
406 #define CFG_DBAT1L CFG_IBAT1L
407 #define CFG_DBAT1U CFG_IBAT1U
409 /* NAND: cache-inhibit and guarded */
410 #define CFG_IBAT2L (CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
412 #define CFG_IBAT2U (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
413 #define CFG_DBAT2L CFG_IBAT2L
414 #define CFG_DBAT2U CFG_IBAT2U
416 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
417 #define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
418 #define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
419 #define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
420 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
421 #define CFG_DBAT3U CFG_IBAT3U
423 /* Stack in dcache: cacheable, no memory coherence */
424 #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
425 #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
426 #define CFG_DBAT4L CFG_IBAT4L
427 #define CFG_DBAT4U CFG_IBAT4U
429 #define CFG_IBAT5L (CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
431 #define CFG_IBAT5U (CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
432 #define CFG_DBAT5L CFG_IBAT5L
433 #define CFG_DBAT5U CFG_IBAT5U
436 /* PCI MEM space: cacheable */
437 #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
438 #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
439 #define CFG_DBAT6L CFG_IBAT6L
440 #define CFG_DBAT6U CFG_IBAT6U
441 /* PCI MMIO space: cache-inhibit and guarded */
442 #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
443 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
444 #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
445 #define CFG_DBAT7L CFG_IBAT7L
446 #define CFG_DBAT7U CFG_IBAT7U
447 #else /* CONFIG_PCI */
448 #define CFG_IBAT6L (0)
449 #define CFG_IBAT6U (0)
450 #define CFG_IBAT7L (0)
451 #define CFG_IBAT7U (0)
452 #define CFG_DBAT6L CFG_IBAT6L
453 #define CFG_DBAT6U CFG_IBAT6U
454 #define CFG_DBAT7L CFG_IBAT7L
455 #define CFG_DBAT7U CFG_IBAT7U
456 #endif /* CONFIG_PCI */
459 * Internal Definitions
463 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
464 #define BOOTFLAG_WARM 0x02 /* Software reboot */
466 #if defined(CONFIG_CMD_KGDB)
467 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
468 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
472 * Environment Configuration
474 #define CONFIG_ENV_OVERWRITE
476 #if defined(CONFIG_UEC_ETH)
477 #define CONFIG_HAS_ETH0
478 #define CONFIG_HAS_ETH1
479 #define CONFIG_HAS_ETH2
480 #define CONFIG_HAS_ETH3
481 #define CONFIG_ETHADDR 00:04:9f:ef:01:01
482 #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
483 #define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
484 #define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
487 #define CONFIG_BAUDRATE 115200
489 #define CONFIG_LOADADDR a00000
490 #define CONFIG_HOSTNAME mpc8360erdk
491 #define CONFIG_BOOTFILE uImage
493 #define CONFIG_IPADDR 10.0.0.99
494 #define CONFIG_SERVERIP 10.0.0.2
495 #define CONFIG_GATEWAYIP 10.0.0.2
496 #define CONFIG_NETMASK 255.255.255.0
497 #define CONFIG_ROOTPATH /nfsroot/
499 #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
500 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
502 #define CONFIG_EXTRA_ENV_SETTINGS \
504 "consoledev=ttyS0\0"\
510 "ubootfile=u-boot.bin\0"\
511 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
512 "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
513 "$mtdparts panic=1\0"\
514 "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
515 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
516 "$gatewayip:$netmask:$hostname:$netdev:off "\
517 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
518 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
519 "rootfstype=jffs2 rw\0"\
520 "tftp_get_uboot=tftp 100000 $ubootfile\0"\
521 "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
522 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
523 "tftp_get_fs=tftp c00000 $fsfile\0"\
524 "nand_erase_kernel=nand erase 0 400000\0"\
525 "nand_erase_dtb=nand erase 400000 20000\0"\
526 "nand_erase_fs=nand erase 420000 3be0000\0"\
527 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
528 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
529 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
530 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
531 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
532 "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
533 "cp.b 100000 ff800000 $filesize\0"\
534 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
535 "nand_write_kernel\0"\
536 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
537 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
538 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
540 "boot_m=bootm $loadaddr - $fdtaddr\0"\
541 "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
543 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
545 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
549 #define CONFIG_BOOTCOMMAND "run dhcpboot"
551 #endif /* __CONFIG_H */