2 * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
17 #define CONFIG_MPC83xx 1 /* MPC83xx family */
18 #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
19 #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
23 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
24 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
29 #ifdef CONFIG_CLKIN_33MHZ
30 #ifdef CONFIG_PCISLAVE
31 #define CONFIG_83XX_PCICLK 33330000 /* in HZ */
33 #define CONFIG_83XX_CLKIN 33330000 /* in Hz */
36 #ifndef CONFIG_SYS_CLK_FREQ
37 #define CONFIG_SYS_CLK_FREQ 33330000
40 #elif defined(CONFIG_CLKIN_66MHZ)
41 #ifdef CONFIG_PCISLAVE
42 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
44 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
47 #ifndef CONFIG_SYS_CLK_FREQ
48 #define CONFIG_SYS_CLK_FREQ 66000000
51 #error Unknown oscillator frequency.
55 * Hardware Reset Configuration Word
57 #ifdef CONFIG_CLKIN_33MHZ
58 #define CONFIG_SYS_HRCW_LOW (\
59 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
60 HRCWL_DDR_TO_SCB_CLK_1X1 |\
61 HRCWL_CSB_TO_CLKIN_8X1 |\
63 HRCWL_CE_PLL_VCO_DIV_4 |\
64 HRCWL_CE_PLL_DIV_1X1 |\
65 HRCWL_CE_TO_PLL_1X15 |\
66 HRCWL_CORE_TO_CSB_2X1)
67 #elif defined(CONFIG_CLKIN_66MHZ)
68 #define CONFIG_SYS_HRCW_LOW (\
69 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
70 HRCWL_DDR_TO_SCB_CLK_1X1 |\
71 HRCWL_CSB_TO_CLKIN_4X1 |\
73 HRCWL_CE_PLL_VCO_DIV_4 |\
74 HRCWL_CE_PLL_DIV_1X1 |\
75 HRCWL_CE_TO_PLL_1X6 |\
76 HRCWL_CORE_TO_CSB_2X1)
79 #ifdef CONFIG_PCISLAVE
80 #define CONFIG_SYS_HRCW_HIGH (\
82 HRCWH_PCI1_ARBITER_DISABLE |\
83 HRCWH_PCICKDRV_DISABLE |\
85 HRCWH_FROM_0XFFF00100 |\
86 HRCWH_BOOTSEQ_DISABLE |\
87 HRCWH_SW_WATCHDOG_DISABLE |\
88 HRCWH_ROM_LOC_LOCAL_16BIT)
90 #define CONFIG_SYS_HRCW_HIGH (\
92 HRCWH_PCI1_ARBITER_ENABLE |\
93 HRCWH_PCICKDRV_ENABLE |\
95 HRCWH_FROM_0X00000100 |\
96 HRCWH_BOOTSEQ_DISABLE |\
97 HRCWH_SW_WATCHDOG_DISABLE |\
98 HRCWH_ROM_LOC_LOCAL_16BIT)
104 #define CONFIG_SYS_SICRH 0x00000000
105 #define CONFIG_SYS_SICRL 0x40000000
107 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
108 #define CONFIG_BOARD_EARLY_INIT_R
113 #define CONFIG_SYS_IMMR 0xE0000000
118 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
121 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000)
122 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
123 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
124 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
126 #define CONFIG_SYS_83XX_DDR_USES_CS0
128 #define CONFIG_DDR_ECC /* support DDR ECC function */
129 #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
132 * DDRCDR - DDR Control Driver Register
134 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
136 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
137 #if defined(CONFIG_SPD_EEPROM)
139 * Determine DDR configuration from I2C interface.
141 #define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
144 * Manually set up DDR parameters
146 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
147 #if defined(CONFIG_DDR_II)
148 #define CONFIG_SYS_DDRCDR 0x80080001
149 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
150 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
151 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
152 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
153 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
154 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
155 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
156 #define CONFIG_SYS_DDR_MODE 0x47d00432
157 #define CONFIG_SYS_DDR_MODE2 0x8000c000
158 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
159 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
160 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
162 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
163 | CSCONFIG_ROW_BIT_13 \
164 | CSCONFIG_COL_BIT_9)
165 #define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
166 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
167 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
168 #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
169 #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
170 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
177 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
178 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
179 #define CONFIG_SYS_MEMTEST_END 0x00100000
182 * The reserved memory
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
187 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
188 #define CONFIG_SYS_RAMBOOT
190 #undef CONFIG_SYS_RAMBOOT
193 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
194 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
195 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
198 * Initial RAM Base Address Setup
200 #define CONFIG_SYS_INIT_RAM_LOCK 1
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
203 #define CONFIG_SYS_GBL_DATA_OFFSET \
204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207 * Local Bus Configuration & Clock Setup
209 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
210 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
211 #define CONFIG_SYS_LBC_LBCR 0x00000000
214 * FLASH on the Local Bus
216 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
217 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
218 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
219 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
220 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
221 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
223 /* Window base at flash base */
224 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
225 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
227 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
228 | BR_PS_16 /* 16 bit port */ \
229 | BR_MS_GPCM /* MSEL = GPCM */ \
231 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
241 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
242 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
244 #undef CONFIG_SYS_FLASH_CHECKSUM
247 * BCSR on the Local Bus
249 #define CONFIG_SYS_BCSR 0xF8000000
250 /* Access window base at BCSR base */
251 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
252 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
254 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
258 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
269 * SDRAM on the Local Bus
271 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
272 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
274 #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
276 #ifdef CONFIG_SYS_LB_SDRAM
277 #define CONFIG_SYS_LBLAWBAR2 0
278 #define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB)
280 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
282 * Base Register 2 and Option Register 2 configure SDRAM.
285 * Base address = BR[0:16] = dynamic
286 * port size = 32-bits = BR2[19:20] = 11
287 * no parity checking = BR2[21:22] = 00
288 * SDRAM for MSEL = BR2[24:26] = 011
291 * 0 4 8 12 16 20 24 28
292 * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
295 /* Port size=32bit, MSEL=DRAM */
296 #define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
299 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
302 * 64MB mask for AM, OR2[0:7] = 1111 1100
303 * XAM, OR2[17:18] = 11
304 * 9 columns OR2[19-21] = 010
305 * 13 rows OR2[23-25] = 100
306 * EAD set for extra time OR[31] = 1
308 * 0 4 8 12 16 20 24 28
309 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
312 #define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
314 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
315 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
319 /* LB sdram refresh timer, about 6us */
320 #define CONFIG_SYS_LBC_LSRT 0x32000000
321 /* LB refresh timer prescal, 266MHz/32 */
322 #define CONFIG_SYS_LBC_MRTPR 0x20000000
324 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
327 * SDRAM Controller configuration sequence.
329 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
330 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
331 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
332 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
333 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
338 * Windows to access Platform I/O Boards (PIB) via local bus
340 #define CONFIG_SYS_PIB_BASE 0xF8008000
341 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
343 /* [RFC] This LBLAW only covers the 2nd window (CS5) */
344 #define CONFIG_SYS_LBLAWBAR3_PRELIM \
345 CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
346 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
349 * CS4 on Local Bus, to PIB
351 /* CS4 base address at 0xf8008000 */
352 #define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \
357 #define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \
368 * CS5 on Local Bus, to PIB
370 /* CS5 base address at 0xf8010000 */
371 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \
372 CONFIG_SYS_PIB_WINDOW_SIZE) \
377 #define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \
390 #define CONFIG_CONS_INDEX 1
391 #define CONFIG_SYS_NS16550
392 #define CONFIG_SYS_NS16550_SERIAL
393 #define CONFIG_SYS_NS16550_REG_SIZE 1
394 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
396 #define CONFIG_SYS_BAUDRATE_TABLE \
397 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
399 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
400 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
402 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
403 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
404 /* Use the HUSH parser */
405 #define CONFIG_SYS_HUSH_PARSER
407 /* pass open firmware flat tree */
408 #define CONFIG_OF_LIBFDT 1
409 #define CONFIG_OF_BOARD_SETUP 1
410 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
413 #define CONFIG_HARD_I2C /* I2C with hardware support */
414 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
415 #define CONFIG_FSL_I2C
416 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
417 #define CONFIG_SYS_I2C_SLAVE 0x7F
418 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
419 #define CONFIG_SYS_I2C_OFFSET 0x3000
420 #define CONFIG_SYS_I2C2_OFFSET 0x3100
423 * Config on-board RTC
425 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
426 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
430 * Addresses are mapped 1-1.
432 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
433 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
434 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
435 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
436 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
437 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
438 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
439 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
440 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
442 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
443 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
444 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
448 #define CONFIG_PCI_INDIRECT_BRIDGE
450 #define CONFIG_PCI_PNP /* do pci plug-and-play */
451 #define CONFIG_83XX_PCI_STREAMING
453 #undef CONFIG_EEPRO100
454 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
455 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
457 #endif /* CONFIG_PCI */
460 #define CONFIG_HWCONFIG 1
463 * QE UEC ethernet configuration
465 #define CONFIG_UEC_ETH
466 #define CONFIG_ETHPRIME "UEC0"
467 #define CONFIG_PHY_MODE_NEED_CHANGE
469 #define CONFIG_UEC_ETH1 /* GETH1 */
471 #ifdef CONFIG_UEC_ETH1
472 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
473 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
474 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
475 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
476 #define CONFIG_SYS_UEC1_PHY_ADDR 0
477 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
478 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
481 #define CONFIG_UEC_ETH2 /* GETH2 */
483 #ifdef CONFIG_UEC_ETH2
484 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
485 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
486 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
487 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
488 #define CONFIG_SYS_UEC2_PHY_ADDR 1
489 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
490 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
497 #ifndef CONFIG_SYS_RAMBOOT
498 #define CONFIG_ENV_IS_IN_FLASH 1
499 #define CONFIG_ENV_ADDR \
500 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
501 #define CONFIG_ENV_SECT_SIZE 0x20000
502 #define CONFIG_ENV_SIZE 0x2000
504 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
505 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
506 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
507 #define CONFIG_ENV_SIZE 0x2000
510 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
511 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
516 #define CONFIG_BOOTP_BOOTFILESIZE
517 #define CONFIG_BOOTP_BOOTPATH
518 #define CONFIG_BOOTP_GATEWAY
519 #define CONFIG_BOOTP_HOSTNAME
523 * Command line configuration.
525 #include <config_cmd_default.h>
527 #define CONFIG_CMD_PING
528 #define CONFIG_CMD_I2C
529 #define CONFIG_CMD_ASKENV
530 #define CONFIG_CMD_SDRAM
532 #if defined(CONFIG_PCI)
533 #define CONFIG_CMD_PCI
536 #if defined(CONFIG_SYS_RAMBOOT)
537 #undef CONFIG_CMD_SAVEENV
538 #undef CONFIG_CMD_LOADS
542 #undef CONFIG_WATCHDOG /* watchdog disabled */
545 * Miscellaneous configurable options
547 #define CONFIG_SYS_LONGHELP /* undef to save memory */
548 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
549 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
551 #if defined(CONFIG_CMD_KGDB)
552 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
554 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
557 /* Print Buffer Size */
558 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
559 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
560 /* Boot Argument Buffer Size */
561 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
562 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
565 * For booting Linux, the board info and command line data
566 * have to be in the first 256 MB of memory, since this is
567 * the maximum mapped by the Linux kernel during initialization.
569 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
574 #define CONFIG_SYS_HID0_INIT 0x000000000
575 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
576 HID0_ENABLE_INSTRUCTION_CACHE)
577 #define CONFIG_SYS_HID2 HID2_HBE
583 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
584 #define CONFIG_BAT_RW
586 /* DDR/LBC SDRAM: cacheable */
587 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
590 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
594 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
595 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
597 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
598 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
600 | BATL_CACHEINHIBIT \
601 | BATL_GUARDEDSTORAGE)
602 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
606 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
607 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
609 /* BCSR: cache-inhibit and guarded */
610 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
612 | BATL_CACHEINHIBIT \
613 | BATL_GUARDEDSTORAGE)
614 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
618 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
619 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
621 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
622 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
625 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
629 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
631 | BATL_CACHEINHIBIT \
632 | BATL_GUARDEDSTORAGE)
633 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
635 /* DDR/LBC SDRAM next 256M: cacheable */
636 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \
639 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \
643 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
644 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
646 /* Stack in dcache: cacheable, no memory coherence */
647 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
648 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
652 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
653 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
656 /* PCI MEM space: cacheable */
657 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
660 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
664 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
665 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
666 /* PCI MMIO space: cache-inhibit and guarded */
667 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
669 | BATL_CACHEINHIBIT \
670 | BATL_GUARDEDSTORAGE)
671 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
675 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
676 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
678 #define CONFIG_SYS_IBAT6L (0)
679 #define CONFIG_SYS_IBAT6U (0)
680 #define CONFIG_SYS_IBAT7L (0)
681 #define CONFIG_SYS_IBAT7U (0)
682 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
683 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
684 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
685 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
688 #if defined(CONFIG_CMD_KGDB)
689 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
690 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
694 * Environment Configuration
697 #define CONFIG_ENV_OVERWRITE
699 #if defined(CONFIG_UEC_ETH)
700 #define CONFIG_HAS_ETH0
701 #define CONFIG_HAS_ETH1
704 #define CONFIG_BAUDRATE 115200
706 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
708 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
709 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
711 #define CONFIG_EXTRA_ENV_SETTINGS \
713 "consoledev=ttyS0\0" \
714 "ramdiskaddr=1000000\0" \
715 "ramdiskfile=ramfs.83xx\0" \
717 "fdtfile=mpc836x_mds.dtb\0" \
720 #define CONFIG_NFSBOOTCOMMAND \
721 "setenv bootargs root=/dev/nfs rw " \
722 "nfsroot=$serverip:$rootpath " \
723 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr - $fdtaddr"
730 #define CONFIG_RAMBOOTCOMMAND \
731 "setenv bootargs root=/dev/ram rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \
733 "tftp $ramdiskaddr $ramdiskfile;" \
734 "tftp $loadaddr $bootfile;" \
735 "tftp $fdtaddr $fdtfile;" \
736 "bootm $loadaddr $ramdiskaddr $fdtaddr"
739 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
741 #endif /* __CONFIG_H */