2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
35 0xF001_0000-0xF001_FFFF Local bus expansion slot
36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
42 Bus Addr Part No. Description Length Location
43 ----------------------------------------------------------------
44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
46 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
59 #if (TEXT_BASE == 0xFE000000)
64 * High Level Configuration Options
66 #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
67 #define CONFIG_MPC8349 /* MPC8349 specific */
69 #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
72 /* On-board devices */
74 #ifdef CONFIG_MPC8349ITX
75 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
76 #define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
80 #define CONFIG_RTC_DS1337
81 #define CONFIG_HARD_I2C
82 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
85 * Device configurations
89 #ifdef CONFIG_HARD_I2C
91 #define CONFIG_MISC_INIT_F
92 #define CONFIG_MISC_INIT_R
94 #define CONFIG_FSL_I2C
95 #define CONFIG_I2C_MULTI_BUS
96 #define CONFIG_I2C_CMD_TREE
97 #define CFG_I2C_OFFSET 0x3000
98 #define CFG_I2C2_OFFSET 0x3100
99 #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */
101 #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
102 #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
103 #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
104 #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
105 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
106 #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
107 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
109 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
110 #define CFG_I2C_SLAVE 0x7F
112 /* Don't probe these addresses: */
113 #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \
114 {1, CFG_I2C_8574_ADDR2}, \
115 {1, CFG_I2C_8574A_ADDR1}, \
116 {1, CFG_I2C_8574A_ADDR2}}
117 /* Bit definitions for the 8574[A] I2C expander */
118 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
119 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
120 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
121 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
122 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
124 #undef CONFIG_SOFT_I2C
129 #ifdef CONFIG_COMPACT_FLASH
131 #define CFG_IDE_MAXBUS 1
132 #define CFG_IDE_MAXDEVICE 1
134 #define CFG_ATA_IDE0_OFFSET 0x0000
135 #define CFG_ATA_BASE_ADDR CFG_CF_BASE
136 #define CFG_ATA_DATA_OFFSET 0x0000
137 #define CFG_ATA_REG_OFFSET 0
138 #define CFG_ATA_ALT_OFFSET 0x0200
139 #define CFG_ATA_STRIDE 2
141 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
143 #define CONFIG_DOS_PARTITION
150 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
151 #define CFG_SDRAM_BASE CFG_DDR_BASE
152 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
153 #define CFG_83XX_DDR_USES_CS0
154 #define CFG_MEMTEST_START 0x1000 /* memtest region */
155 #define CFG_MEMTEST_END 0x2000
157 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
158 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
160 #ifdef CONFIG_HARD_I2C
161 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
164 #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
165 #define CFG_DDR_SIZE 256 /* Mb */
166 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
168 #define CFG_DDR_TIMING_1 0x26242321
169 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
173 *Flash on the Local Bus
176 #define CFG_FLASH_CFI /* use the Common Flash Interface */
177 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
178 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
179 #define CFG_FLASH_EMPTY_INFO
180 #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
181 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
183 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
185 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
186 boards, we say we have two, but don't display a message if we find only one. */
187 #define CFG_FLASH_QUIET_TEST
188 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
189 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
190 #define CFG_FLASH_SIZE 16 /* FLASH size in MB */
191 #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
194 * BRx, ORx, LBLAWBARx, and LBLAWARx
199 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
200 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
201 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
202 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
203 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
204 #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
208 #ifdef CONFIG_VSC7385
210 #define CFG_VSC7385_BASE 0xF8000000
212 #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
213 #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
214 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
215 OR_GPCM_EHTR | OR_GPCM_EAD)
217 #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE
218 #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
224 #define CFG_LED_BASE 0xF9000000
225 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
226 #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
227 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
228 OR_GPCM_EHTR | OR_GPCM_EAD)
232 #ifdef CONFIG_COMPACT_FLASH
234 #define CFG_CF_BASE 0xF0000000
236 #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
237 #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
239 #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE
240 #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
245 * U-Boot memory configuration
247 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
249 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
255 #define CONFIG_L1_INIT_RAM
256 #define CFG_INIT_RAM_LOCK
257 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
258 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
260 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
261 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
262 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
264 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
265 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
268 * Local Bus LCRR and LBCR regs
269 * LCRR: DLL bypass, Clock divider is 4
270 * External Local Bus rate is
271 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
273 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
274 #define CFG_LBC_LBCR 0x00000000
276 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
277 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
282 #define CONFIG_CONS_INDEX 1
283 #undef CONFIG_SERIAL_SOFTWARE_FIFO
285 #define CFG_NS16550_SERIAL
286 #define CFG_NS16550_REG_SIZE 1
287 #define CFG_NS16550_CLK get_bus_freq(0)
289 #define CFG_BAUDRATE_TABLE \
290 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
292 #define CONFIG_CONSOLE ttyS0
293 #define CONFIG_BAUDRATE 115200
295 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
296 #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
298 /* pass open firmware flat tree */
299 #define CONFIG_OF_LIBFDT 1
300 #define CONFIG_OF_BOARD_SETUP
302 #define OF_CPU "PowerPC,8349@0"
303 #define OF_SOC "soc8349@e0000000"
304 #define OF_TBCLK (bd->bi_busfreq / 4)
305 #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
312 #define CONFIG_MPC83XX_PCI2
316 * Addresses are mapped 1-1.
318 #define CFG_PCI1_MEM_BASE 0x80000000
319 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
320 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
321 #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
322 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
323 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
324 #define CFG_PCI1_IO_BASE 0x00000000
325 #define CFG_PCI1_IO_PHYS 0xE2000000
326 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
328 #ifdef CONFIG_MPC83XX_PCI2
329 #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE)
330 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
331 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
332 #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE)
333 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
334 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
335 #define CFG_PCI2_IO_BASE 0x00000000
336 #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE)
337 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
340 #define _IO_BASE 0x00000000 /* points to PCI I/O space */
342 #define CONFIG_NET_MULTI
343 #define CONFIG_PCI_PNP /* do pci plug-and-play */
345 #ifdef CONFIG_RTL8139
346 /* This macro is used by RTL8139 but not defined in PPC architecture */
347 #define KSEG1ADDR(x) (x)
350 #ifndef CONFIG_PCI_PNP
351 #define PCI_ENET0_IOADDR 0x00000000
352 #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE
353 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
356 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
362 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */
364 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
369 #ifdef CONFIG_TSEC_ENET
371 #define CONFIG_NET_MULTI
373 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
378 #define CONFIG_HAS_ETH0
379 #define CONFIG_TSEC1_NAME "TSEC0"
380 #define CFG_TSEC1_OFFSET 0x24000
381 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
382 #define TSEC1_PHYIDX 0
383 #define TSEC1_FLAGS TSEC_GIGABIT
387 #define CONFIG_HAS_ETH1
388 #define CONFIG_TSEC2_NAME "TSEC1"
389 #define CFG_TSEC2_OFFSET 0x25000
390 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
391 #define TSEC2_PHY_ADDR 4
392 #define TSEC2_PHYIDX 0
393 #define TSEC2_FLAGS TSEC_GIGABIT
396 #define CONFIG_ETHPRIME "Freescale TSEC"
403 #define CONFIG_ENV_OVERWRITE
406 #define CFG_ENV_IS_IN_FLASH
407 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
408 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
409 #define CFG_ENV_SIZE 0x2000
411 #define CFG_NO_FLASH /* Flash is not usable now */
412 #undef CFG_FLASH_CFI_DRIVER
413 #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */
414 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
415 #define CFG_ENV_SIZE 0x2000
418 #define CONFIG_LOADS_ECHO /* echo on for serial download */
419 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
424 #define CONFIG_BOOTP_BOOTFILESIZE
425 #define CONFIG_BOOTP_BOOTPATH
426 #define CONFIG_BOOTP_GATEWAY
427 #define CONFIG_BOOTP_HOSTNAME
431 * Command line configuration.
433 #include <config_cmd_default.h>
435 #define CONFIG_CMD_CACHE
436 #define CONFIG_CMD_DATE
437 #define CONFIG_CMD_IRQ
438 #define CONFIG_CMD_NET
439 #define CONFIG_CMD_PING
440 #define CONFIG_CMD_SDRAM
442 #ifdef CONFIG_COMPACT_FLASH
443 #define CONFIG_CMD_IDE
444 #define CONFIG_CMD_FAT
448 #define CONFIG_CMD_PCI
451 #ifdef CONFIG_HARD_I2C
452 #define CONFIG_CMD_I2C
456 #undef CONFIG_WATCHDOG /* watchdog disabled */
459 * Miscellaneous configurable options
461 #define CFG_LONGHELP /* undef to save memory */
462 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
463 #define CFG_HUSH_PARSER /* Use the HUSH parser */
464 #define CFG_PROMPT_HUSH_PS2 "> "
466 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
467 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
469 #ifdef CONFIG_MPC8349ITX
470 #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
472 #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
475 #if defined(CONFIG_CMD_KGDB)
476 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
478 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
481 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
482 #define CFG_MAXARGS 16 /* max number of command args */
483 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
484 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
487 * For booting Linux, the board info and command line data
488 * have to be in the first 8 MB of memory, since this is
489 * the maximum mapped by the Linux kernel during initialization.
491 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
494 * Cache Configuration
496 #define CFG_DCACHE_SIZE 32768
497 #define CFG_CACHELINE_SIZE 32
498 #if defined(CONFIG_CMD_KGDB)
499 #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
502 #define CFG_HRCW_LOW (\
503 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
504 HRCWL_DDR_TO_SCB_CLK_1X1 |\
505 HRCWL_CSB_TO_CLKIN_4X1 |\
507 HRCWL_CORE_TO_CSB_2X1)
510 #define CFG_HRCW_HIGH (\
513 HRCWH_PCI1_ARBITER_ENABLE |\
514 HRCWH_PCI2_ARBITER_ENABLE |\
516 HRCWH_FROM_0X00000100 |\
517 HRCWH_BOOTSEQ_DISABLE |\
518 HRCWH_SW_WATCHDOG_DISABLE |\
519 HRCWH_ROM_LOC_LOCAL_16BIT |\
520 HRCWH_TSEC1M_IN_GMII |\
521 HRCWH_TSEC2M_IN_GMII )
523 #define CFG_HRCW_HIGH (\
526 HRCWH_PCI1_ARBITER_ENABLE |\
527 HRCWH_PCI2_ARBITER_ENABLE |\
529 HRCWH_FROM_0XFFF00100 |\
530 HRCWH_BOOTSEQ_DISABLE |\
531 HRCWH_SW_WATCHDOG_DISABLE |\
532 HRCWH_ROM_LOC_LOCAL_16BIT |\
533 HRCWH_TSEC1M_IN_GMII |\
534 HRCWH_TSEC2M_IN_GMII )
540 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
541 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
542 #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
543 #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
544 #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
545 #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
550 #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
551 #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
553 #define CFG_HID0_INIT 0x000000000
554 #define CFG_HID0_FINAL CFG_HID0_INIT
556 #define CFG_HID2 HID2_HBE
559 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
560 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
564 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
565 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
566 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
567 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
575 #ifdef CONFIG_MPC83XX_PCI2
576 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
577 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
578 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
579 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
587 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
588 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
589 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
591 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
592 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
593 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
598 #define CFG_DBAT0L CFG_IBAT0L
599 #define CFG_DBAT0U CFG_IBAT0U
600 #define CFG_DBAT1L CFG_IBAT1L
601 #define CFG_DBAT1U CFG_IBAT1U
602 #define CFG_DBAT2L CFG_IBAT2L
603 #define CFG_DBAT2U CFG_IBAT2U
604 #define CFG_DBAT3L CFG_IBAT3L
605 #define CFG_DBAT3U CFG_IBAT3U
606 #define CFG_DBAT4L CFG_IBAT4L
607 #define CFG_DBAT4U CFG_IBAT4U
608 #define CFG_DBAT5L CFG_IBAT5L
609 #define CFG_DBAT5U CFG_IBAT5U
610 #define CFG_DBAT6L CFG_IBAT6L
611 #define CFG_DBAT6U CFG_IBAT6U
612 #define CFG_DBAT7L CFG_IBAT7L
613 #define CFG_DBAT7U CFG_IBAT7U
616 * Internal Definitions
620 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
621 #define BOOTFLAG_WARM 0x02 /* Software reboot */
623 #if defined(CONFIG_CMD_KGDB)
624 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
625 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
630 * Environment Configuration
632 #define CONFIG_ENV_OVERWRITE
635 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01
639 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
642 #define CONFIG_IPADDR 192.168.1.253
643 #define CONFIG_SERVERIP 192.168.1.1
644 #define CONFIG_GATEWAYIP 192.168.1.1
645 #define CONFIG_NETMASK 255.255.252.0
646 #define CONFIG_NETDEV eth0
648 #ifdef CONFIG_MPC8349ITX
649 #define CONFIG_HOSTNAME mpc8349emitx
651 #define CONFIG_HOSTNAME mpc8349emitxgp
654 /* Default path and filenames */
655 #define CONFIG_ROOTPATH /nfsroot/rootfs
656 #define CONFIG_BOOTFILE uImage
657 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
659 #ifdef CONFIG_MPC8349ITX
660 #define CONFIG_FDTFILE mpc8349emitx.dtb
662 #define CONFIG_FDTFILE mpc8349emitxgp.dtb
665 #define CONFIG_BOOTDELAY 0
667 #define XMK_STR(x) #x
668 #define MK_STR(x) XMK_STR(x)
670 #define CONFIG_BOOTARGS \
672 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
673 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
674 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
675 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
676 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
678 #define CONFIG_EXTRA_ENV_SETTINGS \
679 "console=" MK_STR(CONFIG_CONSOLE) "\0" \
680 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
681 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
682 "tftpflash=tftpboot $loadaddr $uboot; " \
683 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
684 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
685 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
686 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
687 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
689 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
691 #define CONFIG_NFSBOOTCOMMAND \
692 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
693 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
694 " console=$console,$baudrate $othbootargs; " \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
699 #define CONFIG_RAMBOOTCOMMAND \
700 "setenv bootargs root=/dev/ram rw" \
701 " console=$console,$baudrate $othbootargs; " \
702 "tftp $ramdiskaddr $ramdiskfile;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"