2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * SPDX-License-Identifier: GPL-2.0+
8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
19 0xF001_0000-0xF001_FFFF Local bus expansion slot
20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
26 Bus Addr Part No. Description Length Location
27 ----------------------------------------------------------------
28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
30 I2C1 0x20 PCF8574 I2C Expander 0 U8
31 I2C1 0x21 PCF8574 I2C Expander 0 U10
32 I2C1 0x38 PCF8574A I2C Expander 0 U8
33 I2C1 0x39 PCF8574A I2C Expander 0 U10
34 I2C1 0x51 (DDR) DDR EEPROM 1 U1
35 I2C1 0x68 DS1339 RTC 1 U68
37 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
43 #define CONFIG_SYS_GENERIC_BOARD
44 #define CONFIG_DISPLAY_BOARDINFO
46 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
47 #define CONFIG_SYS_LOWBOOT
51 * High Level Configuration Options
53 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
54 #define CONFIG_MPC8349 /* MPC8349 specific */
56 #ifndef CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_TEXT_BASE 0xFEF00000
60 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
62 #define CONFIG_MISC_INIT_F
63 #define CONFIG_MISC_INIT_R
69 #ifdef CONFIG_MPC8349ITX
70 /* The CF card interface on the back of the board */
71 #define CONFIG_COMPACT_FLASH
72 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
73 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
74 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
78 #define CONFIG_RTC_DS1337
79 #define CONFIG_SYS_I2C
80 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
83 * Device configurations
88 #define CONFIG_SYS_I2C_FSL
89 #define CONFIG_SYS_FSL_I2C_SPEED 400000
90 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
91 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
92 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
93 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
94 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
96 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
97 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
99 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
100 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
101 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
102 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
103 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
104 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
105 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
107 /* Don't probe these addresses: */
108 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
109 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
110 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
111 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
112 /* Bit definitions for the 8574[A] I2C expander */
113 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
114 #define I2C_8574_REVISION 0x03
115 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
116 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
117 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
118 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
123 #ifdef CONFIG_COMPACT_FLASH
125 #define CONFIG_SYS_IDE_MAXBUS 1
126 #define CONFIG_SYS_IDE_MAXDEVICE 1
128 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
129 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
130 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
131 #define CONFIG_SYS_ATA_REG_OFFSET 0
132 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
133 #define CONFIG_SYS_ATA_STRIDE 2
135 /* If a CF card is not inserted, time out quickly */
136 #define ATA_RESET_TIME 1
143 #ifdef CONFIG_SATA_SIL3114
145 #define CONFIG_SYS_SATA_MAX_DEVICE 4
146 #define CONFIG_LIBATA
151 #ifdef CONFIG_SYS_USB_HOST
155 #define CONFIG_CMD_USB
156 #define CONFIG_USB_STORAGE
157 #define CONFIG_USB_EHCI
158 #define CONFIG_USB_EHCI_FSL
160 /* Current USB implementation supports the only USB controller,
161 * so we have to choose between the MPH or the DR ones */
163 #define CONFIG_HAS_FSL_MPH_USB
165 #define CONFIG_HAS_FSL_DR_USB
173 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
175 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
176 #define CONFIG_SYS_83XX_DDR_USES_CS0
177 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
178 #define CONFIG_SYS_MEMTEST_END 0x2000
180 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
181 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
183 #define CONFIG_VERY_BIG_RAM
184 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
186 #ifdef CONFIG_SYS_I2C
187 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
190 /* No SPD? Then manually set up DDR parameters */
191 #ifndef CONFIG_SPD_EEPROM
192 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
193 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
194 | CSCONFIG_ROW_BIT_13 \
195 | CSCONFIG_COL_BIT_10)
197 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
198 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
202 *Flash on the Local Bus
205 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
206 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
207 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
208 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 /* 127 64KB sectors + 8 8KB sectors per device */
210 #define CONFIG_SYS_MAX_FLASH_SECT 135
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
213 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
215 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
216 boards, we say we have two, but don't display a message if we find only one. */
217 #define CONFIG_SYS_FLASH_QUIET_TEST
218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
219 #define CONFIG_SYS_FLASH_BANKS_LIST \
220 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
221 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
222 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
226 #ifdef CONFIG_VSC7385_ENET
230 /* The flash address and size of the VSC7385 firmware image */
231 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
232 #define CONFIG_VSC7385_IMAGE_SIZE 8192
237 * BRx, ORx, LBLAWBARx, and LBLAWARx
242 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
246 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
255 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
256 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
260 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
262 #ifdef CONFIG_VSC7385_ENET
264 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
268 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
277 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
278 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
284 #define CONFIG_SYS_LED_BASE 0xF9000000
285 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
289 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
300 #ifdef CONFIG_COMPACT_FLASH
302 #define CONFIG_SYS_CF_BASE 0xF0000000
304 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
308 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
310 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
311 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
316 * U-Boot memory configuration
318 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
320 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
321 #define CONFIG_SYS_RAMBOOT
323 #undef CONFIG_SYS_RAMBOOT
326 #define CONFIG_SYS_INIT_RAM_LOCK
327 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
328 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
330 #define CONFIG_SYS_GBL_DATA_OFFSET \
331 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
332 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
334 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
335 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
336 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
339 * Local Bus LCRR and LBCR regs
340 * LCRR: DLL bypass, Clock divider is 4
341 * External Local Bus rate is
342 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
344 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
345 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
346 #define CONFIG_SYS_LBC_LBCR 0x00000000
348 /* LB sdram refresh timer, about 6us */
349 #define CONFIG_SYS_LBC_LSRT 0x32000000
350 /* LB refresh timer prescal, 266MHz/32*/
351 #define CONFIG_SYS_LBC_MRTPR 0x20000000
356 #define CONFIG_CONS_INDEX 1
357 #define CONFIG_SYS_NS16550
358 #define CONFIG_SYS_NS16550_SERIAL
359 #define CONFIG_SYS_NS16550_REG_SIZE 1
360 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
362 #define CONFIG_SYS_BAUDRATE_TABLE \
363 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
365 #define CONFIG_CONSOLE ttyS0
366 #define CONFIG_BAUDRATE 115200
368 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
369 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
371 /* pass open firmware flat tree */
372 #define CONFIG_OF_LIBFDT 1
373 #define CONFIG_OF_BOARD_SETUP 1
374 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
380 #define CONFIG_PCI_INDIRECT_BRIDGE
382 #define CONFIG_MPC83XX_PCI2
386 * Addresses are mapped 1-1.
388 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
389 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
390 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
391 #define CONFIG_SYS_PCI1_MMIO_BASE \
392 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
393 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
394 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
395 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
396 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
397 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
399 #ifdef CONFIG_MPC83XX_PCI2
400 #define CONFIG_SYS_PCI2_MEM_BASE \
401 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
402 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
403 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
404 #define CONFIG_SYS_PCI2_MMIO_BASE \
405 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
406 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
407 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
408 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
409 #define CONFIG_SYS_PCI2_IO_PHYS \
410 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
411 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
414 #define CONFIG_PCI_PNP /* do pci plug-and-play */
416 #ifndef CONFIG_PCI_PNP
417 #define PCI_ENET0_IOADDR 0x00000000
418 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
419 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
422 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
426 #define CONFIG_PCI_66M
427 #ifdef CONFIG_PCI_66M
428 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */
430 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
435 #ifdef CONFIG_TSEC_ENET
438 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
443 #define CONFIG_HAS_ETH0
444 #define CONFIG_TSEC1_NAME "TSEC0"
445 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
446 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
447 #define TSEC1_PHYIDX 0
448 #define TSEC1_FLAGS TSEC_GIGABIT
452 #define CONFIG_HAS_ETH1
453 #define CONFIG_TSEC2_NAME "TSEC1"
454 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
456 #define TSEC2_PHY_ADDR 4
457 #define TSEC2_PHYIDX 0
458 #define TSEC2_FLAGS TSEC_GIGABIT
461 #define CONFIG_ETHPRIME "Freescale TSEC"
468 #define CONFIG_ENV_OVERWRITE
470 #ifndef CONFIG_SYS_RAMBOOT
471 #define CONFIG_ENV_IS_IN_FLASH
472 #define CONFIG_ENV_ADDR \
473 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
474 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
475 #define CONFIG_ENV_SIZE 0x2000
477 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
478 #undef CONFIG_FLASH_CFI_DRIVER
479 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
480 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
481 #define CONFIG_ENV_SIZE 0x2000
484 #define CONFIG_LOADS_ECHO /* echo on for serial download */
485 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
490 #define CONFIG_BOOTP_BOOTFILESIZE
491 #define CONFIG_BOOTP_BOOTPATH
492 #define CONFIG_BOOTP_GATEWAY
493 #define CONFIG_BOOTP_HOSTNAME
497 * Command line configuration.
499 #define CONFIG_CMD_CACHE
500 #define CONFIG_CMD_DATE
501 #define CONFIG_CMD_IRQ
502 #define CONFIG_CMD_PING
503 #define CONFIG_CMD_DHCP
504 #define CONFIG_CMD_SDRAM
506 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
507 || defined(CONFIG_USB_STORAGE)
508 #define CONFIG_DOS_PARTITION
509 #define CONFIG_CMD_FAT
510 #define CONFIG_SUPPORT_VFAT
513 #ifdef CONFIG_COMPACT_FLASH
514 #define CONFIG_CMD_IDE
517 #ifdef CONFIG_SATA_SIL3114
518 #define CONFIG_CMD_SATA
521 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
522 #define CONFIG_CMD_EXT2
526 #define CONFIG_CMD_PCI
529 #ifdef CONFIG_SYS_I2C
530 #define CONFIG_CMD_I2C
534 #undef CONFIG_WATCHDOG /* watchdog disabled */
537 * Miscellaneous configurable options
539 #define CONFIG_SYS_LONGHELP /* undef to save memory */
540 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
541 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
542 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
544 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
545 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
547 #ifdef CONFIG_MPC8349ITX
548 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
550 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
553 #if defined(CONFIG_CMD_KGDB)
554 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
556 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
559 /* Print Buffer Size */
560 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
561 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
562 /* Boot Argument Buffer Size */
563 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
566 * For booting Linux, the board info and command line data
567 * have to be in the first 256 MB of memory, since this is
568 * the maximum mapped by the Linux kernel during initialization.
570 /* Initial Memory map for Linux*/
571 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
573 #define CONFIG_SYS_HRCW_LOW (\
574 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
575 HRCWL_DDR_TO_SCB_CLK_1X1 |\
576 HRCWL_CSB_TO_CLKIN_4X1 |\
578 HRCWL_CORE_TO_CSB_2X1)
580 #ifdef CONFIG_SYS_LOWBOOT
581 #define CONFIG_SYS_HRCW_HIGH (\
584 HRCWH_PCI1_ARBITER_ENABLE |\
585 HRCWH_PCI2_ARBITER_ENABLE |\
587 HRCWH_FROM_0X00000100 |\
588 HRCWH_BOOTSEQ_DISABLE |\
589 HRCWH_SW_WATCHDOG_DISABLE |\
590 HRCWH_ROM_LOC_LOCAL_16BIT |\
591 HRCWH_TSEC1M_IN_GMII |\
592 HRCWH_TSEC2M_IN_GMII)
594 #define CONFIG_SYS_HRCW_HIGH (\
597 HRCWH_PCI1_ARBITER_ENABLE |\
598 HRCWH_PCI2_ARBITER_ENABLE |\
600 HRCWH_FROM_0XFFF00100 |\
601 HRCWH_BOOTSEQ_DISABLE |\
602 HRCWH_SW_WATCHDOG_DISABLE |\
603 HRCWH_ROM_LOC_LOCAL_16BIT |\
604 HRCWH_TSEC1M_IN_GMII |\
605 HRCWH_TSEC2M_IN_GMII)
611 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
612 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
613 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
614 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
615 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
616 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
617 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
618 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
623 /* Needed for gigabit to work on TSEC 1 */
624 #define CONFIG_SYS_SICRH SICRH_TSOBI1
625 /* USB DR as device + USB MPH as host */
626 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
628 #define CONFIG_SYS_HID0_INIT 0x00000000
629 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
631 #define CONFIG_SYS_HID2 HID2_HBE
632 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
635 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
638 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
645 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
648 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
652 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
654 | BATL_CACHEINHIBIT \
655 | BATL_GUARDEDSTORAGE)
656 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
661 #define CONFIG_SYS_IBAT1L 0
662 #define CONFIG_SYS_IBAT1U 0
663 #define CONFIG_SYS_IBAT2L 0
664 #define CONFIG_SYS_IBAT2U 0
667 #ifdef CONFIG_MPC83XX_PCI2
668 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
671 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
675 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
677 | BATL_CACHEINHIBIT \
678 | BATL_GUARDEDSTORAGE)
679 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
684 #define CONFIG_SYS_IBAT3L 0
685 #define CONFIG_SYS_IBAT3U 0
686 #define CONFIG_SYS_IBAT4L 0
687 #define CONFIG_SYS_IBAT4U 0
690 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
691 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
693 | BATL_CACHEINHIBIT \
694 | BATL_GUARDEDSTORAGE)
695 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
700 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
701 #define CONFIG_SYS_IBAT6L (0xF0000000 \
703 | BATL_MEMCOHERENCE \
704 | BATL_GUARDEDSTORAGE)
705 #define CONFIG_SYS_IBAT6U (0xF0000000 \
710 #define CONFIG_SYS_IBAT7L 0
711 #define CONFIG_SYS_IBAT7U 0
713 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
714 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
715 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
716 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
717 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
718 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
719 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
720 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
721 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
722 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
723 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
724 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
725 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
726 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
727 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
728 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
730 #if defined(CONFIG_CMD_KGDB)
731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
736 * Environment Configuration
738 #define CONFIG_ENV_OVERWRITE
740 #define CONFIG_NETDEV "eth0"
742 #ifdef CONFIG_MPC8349ITX
743 #define CONFIG_HOSTNAME "mpc8349emitx"
745 #define CONFIG_HOSTNAME "mpc8349emitxgp"
748 /* Default path and filenames */
749 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
750 #define CONFIG_BOOTFILE "uImage"
751 /* U-Boot image on TFTP server */
752 #define CONFIG_UBOOTPATH "u-boot.bin"
754 #ifdef CONFIG_MPC8349ITX
755 #define CONFIG_FDTFILE "mpc8349emitx.dtb"
757 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
760 #define CONFIG_BOOTDELAY 6
762 #define CONFIG_BOOTARGS \
764 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
765 " ip=" __stringify(CONFIG_IPADDR) ":" \
766 __stringify(CONFIG_SERVERIP) ":" \
767 __stringify(CONFIG_GATEWAYIP) ":" \
768 __stringify(CONFIG_NETMASK) ":" \
769 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
770 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
772 #define CONFIG_EXTRA_ENV_SETTINGS \
773 "console=" __stringify(CONFIG_CONSOLE) "\0" \
774 "netdev=" CONFIG_NETDEV "\0" \
775 "uboot=" CONFIG_UBOOTPATH "\0" \
776 "tftpflash=tftpboot $loadaddr $uboot; " \
777 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
779 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
781 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
783 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
785 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
788 "fdtfile=" CONFIG_FDTFILE "\0"
790 #define CONFIG_NFSBOOTCOMMAND \
791 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
792 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
793 " console=$console,$baudrate $othbootargs; " \
794 "tftp $loadaddr $bootfile;" \
795 "tftp $fdtaddr $fdtfile;" \
796 "bootm $loadaddr - $fdtaddr"
798 #define CONFIG_RAMBOOTCOMMAND \
799 "setenv bootargs root=/dev/ram rw" \
800 " console=$console,$baudrate $othbootargs; " \
801 "tftp $ramdiskaddr $ramdiskfile;" \
802 "tftp $loadaddr $bootfile;" \
803 "tftp $fdtaddr $fdtfile;" \
804 "bootm $loadaddr $ramdiskaddr $fdtaddr"