1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #define CONFIG_PCI_66M
22 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
24 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
27 #ifdef CONFIG_PCISLAVE
28 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */
29 #endif /* CONFIG_PCISLAVE */
31 #ifndef CONFIG_SYS_CLK_FREQ
33 #define CONFIG_SYS_CLK_FREQ 66000000
34 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
36 #define CONFIG_SYS_CLK_FREQ 33000000
37 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
41 #define CONFIG_SYS_IMMR 0xE0000000
43 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
44 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
45 #define CONFIG_SYS_MEMTEST_END 0x00100000
50 #define CONFIG_DDR_ECC /* support DDR ECC function */
51 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
52 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
55 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
56 * unselect it to use old spd_sdram.c
58 #define CONFIG_SYS_SPD_BUS_NUM 0
59 #define SPD_EEPROM_ADDRESS1 0x52
60 #define SPD_EEPROM_ADDRESS2 0x51
61 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
62 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
63 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
64 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
67 * 32-bit data path mode.
69 * Please note that using this mode for devices with the real density of 64-bit
70 * effectively reduces the amount of available memory due to the effect of
71 * wrapping around while translating address to row/columns, for example in the
72 * 256MB module the upper 128MB get aliased with contents of the lower
73 * 128MB); normally this define should be used for devices with real 32-bit
76 #undef CONFIG_DDR_32BIT
78 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
79 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
80 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
81 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
82 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
83 #undef CONFIG_DDR_2T_TIMING
86 * DDRCDR - DDR Control Driver Register
88 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
90 #if defined(CONFIG_SPD_EEPROM)
92 * Determine DDR configuration from I2C interface.
94 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
97 * Manually set up DDR parameters
99 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
100 #if defined(CONFIG_DDR_II)
101 #define CONFIG_SYS_DDRCDR 0x80080001
102 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
103 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
104 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
105 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
106 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
107 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
108 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
109 #define CONFIG_SYS_DDR_MODE 0x47d00432
110 #define CONFIG_SYS_DDR_MODE2 0x8000c000
111 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
112 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
113 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
115 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
116 | CSCONFIG_ROW_BIT_13 \
117 | CSCONFIG_COL_BIT_10)
118 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
120 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
121 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
123 #if defined(CONFIG_DDR_32BIT)
124 /* set burst length to 8 for 32-bit data path */
125 /* DLL,normal,seq,4/2.5, 8 burst len */
126 #define CONFIG_SYS_DDR_MODE 0x00000023
128 /* the default burst length is 4 - for 64-bit data path */
129 /* DLL,normal,seq,4/2.5, 4 burst len */
130 #define CONFIG_SYS_DDR_MODE 0x00000022
136 * SDRAM on the Local Bus
138 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
139 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
142 * FLASH on the Local Bus
144 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
145 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
147 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
148 | BR_PS_16 /* 16 bit port */ \
149 | BR_MS_GPCM /* MSEL = GPCM */ \
151 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
161 /* window base at flash base */
162 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
163 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
165 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
166 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
168 #undef CONFIG_SYS_FLASH_CHECKSUM
169 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
170 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
174 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
175 #define CONFIG_SYS_RAMBOOT
177 #undef CONFIG_SYS_RAMBOOT
181 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
183 #define CONFIG_SYS_BCSR 0xE2400000
184 /* Access window base at BCSR base */
185 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
186 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
187 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
192 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
196 | OR_GPCM_TRLX_CLEAR \
197 | OR_GPCM_EHTR_CLEAR)
200 #define CONFIG_SYS_INIT_RAM_LOCK 1
201 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
204 #define CONFIG_SYS_GBL_DATA_OFFSET \
205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
208 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
212 * Local Bus LCRR and LBCR regs
213 * LCRR: DLL bypass, Clock divider is 4
214 * External Local Bus rate is
215 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
217 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
218 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
219 #define CONFIG_SYS_LBC_LBCR 0x00000000
224 #define CONFIG_SYS_NS16550_SERIAL
225 #define CONFIG_SYS_NS16550_REG_SIZE 1
226 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
228 #define CONFIG_SYS_BAUDRATE_TABLE \
229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
235 #define CONFIG_SYS_I2C
236 #define CONFIG_SYS_I2C_FSL
237 #define CONFIG_SYS_FSL_I2C_SPEED 400000
238 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
239 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
240 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
241 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
242 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
243 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
246 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
248 /* GPIOs. Used as SPI chip selects */
249 #define CONFIG_SYS_GPIO1_PRELIM
250 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
251 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
254 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
255 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
256 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
257 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
260 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
264 * Addresses are mapped 1-1.
266 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
267 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
268 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
269 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
270 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
271 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
272 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
273 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
274 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
276 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
277 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
278 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
279 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
280 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
281 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
282 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
283 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
284 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
286 #if defined(CONFIG_PCI)
289 #if defined(PCI_64BIT)
295 #define CONFIG_83XX_PCI_STREAMING
297 #undef CONFIG_EEPRO100
300 #if !defined(CONFIG_PCI_PNP)
301 #define PCI_ENET0_IOADDR 0xFIXME
302 #define PCI_ENET0_MEMADDR 0xFIXME
303 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
306 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
307 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
309 #endif /* CONFIG_PCI */
315 #if defined(CONFIG_TSEC_ENET)
317 #define CONFIG_GMII 1 /* MII PHY management */
318 #define CONFIG_TSEC1 1
319 #define CONFIG_TSEC1_NAME "TSEC0"
320 #define CONFIG_TSEC2 1
321 #define CONFIG_TSEC2_NAME "TSEC1"
322 #define TSEC1_PHY_ADDR 0
323 #define TSEC2_PHY_ADDR 1
324 #define TSEC1_PHYIDX 0
325 #define TSEC2_PHYIDX 0
326 #define TSEC1_FLAGS TSEC_GIGABIT
327 #define TSEC2_FLAGS TSEC_GIGABIT
329 /* Options are: TSEC[0-1] */
330 #define CONFIG_ETHPRIME "TSEC0"
332 #endif /* CONFIG_TSEC_ENET */
335 * Configure on-board RTC
337 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
343 #ifndef CONFIG_SYS_RAMBOOT
344 #define CONFIG_ENV_ADDR \
345 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
346 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
347 #define CONFIG_ENV_SIZE 0x2000
349 /* Address and size of Redundant Environment Sector */
350 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
351 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
355 #define CONFIG_ENV_SIZE 0x2000
358 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
359 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
364 #define CONFIG_BOOTP_BOOTFILESIZE
367 * Command line configuration.
370 #undef CONFIG_WATCHDOG /* watchdog disabled */
373 * Miscellaneous configurable options
375 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
378 * For booting Linux, the board info and command line data
379 * have to be in the first 256 MB of memory, since this is
380 * the maximum mapped by the Linux kernel during initialization.
382 /* Initial Memory map for Linux*/
383 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
384 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
386 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
389 #define CONFIG_SYS_HRCW_LOW (\
390 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
391 HRCWL_DDR_TO_SCB_CLK_1X1 |\
392 HRCWL_CSB_TO_CLKIN |\
394 HRCWL_CORE_TO_CSB_2X1)
396 #define CONFIG_SYS_HRCW_LOW (\
397 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
398 HRCWL_DDR_TO_SCB_CLK_1X1 |\
399 HRCWL_CSB_TO_CLKIN |\
401 HRCWL_CORE_TO_CSB_3X1)
403 #define CONFIG_SYS_HRCW_LOW (\
404 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
405 HRCWL_DDR_TO_SCB_CLK_1X1 |\
406 HRCWL_CSB_TO_CLKIN |\
408 HRCWL_CORE_TO_CSB_2X1)
410 #define CONFIG_SYS_HRCW_LOW (\
411 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
412 HRCWL_DDR_TO_SCB_CLK_1X1 |\
413 HRCWL_CSB_TO_CLKIN |\
415 HRCWL_CORE_TO_CSB_1X1)
417 #define CONFIG_SYS_HRCW_LOW (\
418 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
419 HRCWL_DDR_TO_SCB_CLK_1X1 |\
420 HRCWL_CSB_TO_CLKIN |\
422 HRCWL_CORE_TO_CSB_1X1)
425 #ifdef CONFIG_PCISLAVE
426 #define CONFIG_SYS_HRCW_HIGH (\
429 HRCWH_PCI1_ARBITER_DISABLE |\
430 HRCWH_PCI2_ARBITER_DISABLE |\
432 HRCWH_FROM_0X00000100 |\
433 HRCWH_BOOTSEQ_DISABLE |\
434 HRCWH_SW_WATCHDOG_DISABLE |\
435 HRCWH_ROM_LOC_LOCAL_16BIT |\
436 HRCWH_TSEC1M_IN_GMII |\
437 HRCWH_TSEC2M_IN_GMII)
439 #if defined(PCI_64BIT)
440 #define CONFIG_SYS_HRCW_HIGH (\
443 HRCWH_PCI1_ARBITER_ENABLE |\
444 HRCWH_PCI2_ARBITER_DISABLE |\
446 HRCWH_FROM_0X00000100 |\
447 HRCWH_BOOTSEQ_DISABLE |\
448 HRCWH_SW_WATCHDOG_DISABLE |\
449 HRCWH_ROM_LOC_LOCAL_16BIT |\
450 HRCWH_TSEC1M_IN_GMII |\
451 HRCWH_TSEC2M_IN_GMII)
453 #define CONFIG_SYS_HRCW_HIGH (\
456 HRCWH_PCI1_ARBITER_ENABLE |\
457 HRCWH_PCI2_ARBITER_ENABLE |\
459 HRCWH_FROM_0X00000100 |\
460 HRCWH_BOOTSEQ_DISABLE |\
461 HRCWH_SW_WATCHDOG_DISABLE |\
462 HRCWH_ROM_LOC_LOCAL_16BIT |\
463 HRCWH_TSEC1M_IN_GMII |\
464 HRCWH_TSEC2M_IN_GMII)
465 #endif /* PCI_64BIT */
466 #endif /* CONFIG_PCISLAVE */
471 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
472 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
473 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
474 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
475 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
476 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
478 /* System IO Config */
479 #define CONFIG_SYS_SICRH 0
480 #define CONFIG_SYS_SICRL SICRL_LDP_A
482 #define CONFIG_SYS_HID0_INIT 0x000000000
483 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
484 | HID0_ENABLE_INSTRUCTION_CACHE)
486 /* #define CONFIG_SYS_HID0_FINAL (\
487 HID0_ENABLE_INSTRUCTION_CACHE |\
489 HID0_ENABLE_ADDRESS_BROADCAST) */
491 #define CONFIG_SYS_HID2 HID2_HBE
492 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
494 /* DDR @ 0x00000000 */
495 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
498 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
503 /* PCI @ 0x80000000 */
505 #define CONFIG_PCI_INDIRECT_BRIDGE
506 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
509 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
513 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
515 | BATL_CACHEINHIBIT \
516 | BATL_GUARDEDSTORAGE)
517 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
522 #define CONFIG_SYS_IBAT1L (0)
523 #define CONFIG_SYS_IBAT1U (0)
524 #define CONFIG_SYS_IBAT2L (0)
525 #define CONFIG_SYS_IBAT2U (0)
528 #ifdef CONFIG_MPC83XX_PCI2
529 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
532 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
536 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
538 | BATL_CACHEINHIBIT \
539 | BATL_GUARDEDSTORAGE)
540 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
545 #define CONFIG_SYS_IBAT3L (0)
546 #define CONFIG_SYS_IBAT3U (0)
547 #define CONFIG_SYS_IBAT4L (0)
548 #define CONFIG_SYS_IBAT4U (0)
551 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
552 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
554 | BATL_CACHEINHIBIT \
555 | BATL_GUARDEDSTORAGE)
556 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
561 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
562 #define CONFIG_SYS_IBAT6L (0xF0000000 \
564 | BATL_MEMCOHERENCE \
565 | BATL_GUARDEDSTORAGE)
566 #define CONFIG_SYS_IBAT6U (0xF0000000 \
571 #define CONFIG_SYS_IBAT7L (0)
572 #define CONFIG_SYS_IBAT7U (0)
574 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
575 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
576 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
577 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
578 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
579 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
580 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
581 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
582 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
583 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
584 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
585 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
586 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
587 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
588 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
589 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
591 #if defined(CONFIG_CMD_KGDB)
592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
596 * Environment Configuration
598 #define CONFIG_ENV_OVERWRITE
600 #if defined(CONFIG_TSEC_ENET)
601 #define CONFIG_HAS_ETH1
602 #define CONFIG_HAS_ETH0
605 #define CONFIG_HOSTNAME "mpc8349emds"
606 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
607 #define CONFIG_BOOTFILE "uImage"
609 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
611 #define CONFIG_PREBOOT "echo;" \
612 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
615 #define CONFIG_EXTRA_ENV_SETTINGS \
617 "hostname=mpc8349emds\0" \
618 "nfsargs=setenv bootargs root=/dev/nfs rw " \
619 "nfsroot=${serverip}:${rootpath}\0" \
620 "ramargs=setenv bootargs root=/dev/ram rw\0" \
621 "addip=setenv bootargs ${bootargs} " \
622 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
623 ":${hostname}:${netdev}:off panic=1\0" \
624 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
625 "flash_nfs=run nfsargs addip addtty;" \
626 "bootm ${kernel_addr}\0" \
627 "flash_self=run ramargs addip addtty;" \
628 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
629 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
631 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
632 "update=protect off fe000000 fe03ffff; " \
633 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
634 "upd=run load update\0" \
636 "fdtfile=mpc834x_mds.dtb\0" \
639 #define CONFIG_NFSBOOTCOMMAND \
640 "setenv bootargs root=/dev/nfs rw " \
641 "nfsroot=$serverip:$rootpath " \
642 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
644 "console=$consoledev,$baudrate $othbootargs;" \
645 "tftp $loadaddr $bootfile;" \
646 "tftp $fdtaddr $fdtfile;" \
647 "bootm $loadaddr - $fdtaddr"
649 #define CONFIG_RAMBOOTCOMMAND \
650 "setenv bootargs root=/dev/ram rw " \
651 "console=$consoledev,$baudrate $othbootargs;" \
652 "tftp $ramdiskaddr $ramdiskfile;" \
653 "tftp $loadaddr $bootfile;" \
654 "tftp $fdtaddr $fdtfile;" \
655 "bootm $loadaddr $ramdiskaddr $fdtaddr"
657 #define CONFIG_BOOTCOMMAND "run flash_self"
659 #endif /* __CONFIG_H */