1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
21 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
22 #define CONFIG_SYS_MEMTEST_END 0x00100000
27 #define CONFIG_DDR_ECC /* support DDR ECC function */
28 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
29 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
32 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
33 * unselect it to use old spd_sdram.c
35 #define CONFIG_SYS_SPD_BUS_NUM 0
36 #define SPD_EEPROM_ADDRESS1 0x52
37 #define SPD_EEPROM_ADDRESS2 0x51
38 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
39 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
40 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
41 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
44 * 32-bit data path mode.
46 * Please note that using this mode for devices with the real density of 64-bit
47 * effectively reduces the amount of available memory due to the effect of
48 * wrapping around while translating address to row/columns, for example in the
49 * 256MB module the upper 128MB get aliased with contents of the lower
50 * 128MB); normally this define should be used for devices with real 32-bit
53 #undef CONFIG_DDR_32BIT
55 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
57 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
58 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
59 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
60 #undef CONFIG_DDR_2T_TIMING
63 * DDRCDR - DDR Control Driver Register
65 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
67 #if defined(CONFIG_SPD_EEPROM)
69 * Determine DDR configuration from I2C interface.
71 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
74 * Manually set up DDR parameters
76 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
77 #if defined(CONFIG_DDR_II)
78 #define CONFIG_SYS_DDRCDR 0x80080001
79 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
80 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
81 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
82 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
83 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
84 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
85 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
86 #define CONFIG_SYS_DDR_MODE 0x47d00432
87 #define CONFIG_SYS_DDR_MODE2 0x8000c000
88 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
89 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
90 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
92 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
93 | CSCONFIG_ROW_BIT_13 \
94 | CSCONFIG_COL_BIT_10)
95 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
96 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
97 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
98 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
100 #if defined(CONFIG_DDR_32BIT)
101 /* set burst length to 8 for 32-bit data path */
102 /* DLL,normal,seq,4/2.5, 8 burst len */
103 #define CONFIG_SYS_DDR_MODE 0x00000023
105 /* the default burst length is 4 - for 64-bit data path */
106 /* DLL,normal,seq,4/2.5, 4 burst len */
107 #define CONFIG_SYS_DDR_MODE 0x00000022
113 * SDRAM on the Local Bus
115 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
116 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
119 * FLASH on the Local Bus
121 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
122 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
125 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
126 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
128 #undef CONFIG_SYS_FLASH_CHECKSUM
129 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
130 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
134 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
135 #define CONFIG_SYS_RAMBOOT
137 #undef CONFIG_SYS_RAMBOOT
141 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
143 #define CONFIG_SYS_BCSR 0xE2400000
144 /* Access window base at BCSR base */
147 #define CONFIG_SYS_INIT_RAM_LOCK 1
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
151 #define CONFIG_SYS_GBL_DATA_OFFSET \
152 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
155 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
156 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
159 * Local Bus LCRR and LBCR regs
160 * LCRR: DLL bypass, Clock divider is 4
161 * External Local Bus rate is
162 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
164 #define CONFIG_SYS_LBC_LBCR 0x00000000
169 #define CONFIG_SYS_NS16550_SERIAL
170 #define CONFIG_SYS_NS16550_REG_SIZE 1
171 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
173 #define CONFIG_SYS_BAUDRATE_TABLE \
174 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
180 #define CONFIG_SYS_I2C
181 #define CONFIG_SYS_I2C_FSL
182 #define CONFIG_SYS_FSL_I2C_SPEED 400000
183 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
184 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
185 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
186 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
188 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
191 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
193 /* GPIOs. Used as SPI chip selects */
194 #define CONFIG_SYS_GPIO1_PRELIM
195 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
196 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
199 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
200 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
201 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
202 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
205 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
209 * Addresses are mapped 1-1.
211 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
212 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
213 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
214 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
215 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
216 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
217 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
218 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
219 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
221 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
222 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
223 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
224 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
225 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
226 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
227 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
228 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
229 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
231 #if defined(CONFIG_PCI)
233 #define CONFIG_83XX_PCI_STREAMING
235 #undef CONFIG_EEPRO100
238 #if !defined(CONFIG_PCI_PNP)
239 #define PCI_ENET0_IOADDR 0xFIXME
240 #define PCI_ENET0_MEMADDR 0xFIXME
241 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
244 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
245 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
247 #endif /* CONFIG_PCI */
253 #if defined(CONFIG_TSEC_ENET)
255 #define CONFIG_GMII 1 /* MII PHY management */
256 #define CONFIG_TSEC1 1
257 #define CONFIG_TSEC1_NAME "TSEC0"
258 #define CONFIG_TSEC2 1
259 #define CONFIG_TSEC2_NAME "TSEC1"
260 #define TSEC1_PHY_ADDR 0
261 #define TSEC2_PHY_ADDR 1
262 #define TSEC1_PHYIDX 0
263 #define TSEC2_PHYIDX 0
264 #define TSEC1_FLAGS TSEC_GIGABIT
265 #define TSEC2_FLAGS TSEC_GIGABIT
267 /* Options are: TSEC[0-1] */
268 #define CONFIG_ETHPRIME "TSEC0"
270 #endif /* CONFIG_TSEC_ENET */
273 * Configure on-board RTC
275 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
276 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
281 #ifndef CONFIG_SYS_RAMBOOT
282 #define CONFIG_ENV_ADDR \
283 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
284 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
285 #define CONFIG_ENV_SIZE 0x2000
287 /* Address and size of Redundant Environment Sector */
288 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
289 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
292 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
293 #define CONFIG_ENV_SIZE 0x2000
296 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
297 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
302 #define CONFIG_BOOTP_BOOTFILESIZE
305 * Command line configuration.
308 #undef CONFIG_WATCHDOG /* watchdog disabled */
311 * Miscellaneous configurable options
313 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
316 * For booting Linux, the board info and command line data
317 * have to be in the first 256 MB of memory, since this is
318 * the maximum mapped by the Linux kernel during initialization.
320 /* Initial Memory map for Linux*/
321 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
322 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
324 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
329 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
330 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
332 /* System IO Config */
333 #define CONFIG_SYS_SICRH 0
334 #define CONFIG_SYS_SICRL SICRL_LDP_A
337 #define CONFIG_PCI_INDIRECT_BRIDGE
340 #if defined(CONFIG_CMD_KGDB)
341 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
345 * Environment Configuration
347 #define CONFIG_ENV_OVERWRITE
349 #if defined(CONFIG_TSEC_ENET)
350 #define CONFIG_HAS_ETH1
351 #define CONFIG_HAS_ETH0
354 #define CONFIG_HOSTNAME "mpc8349emds"
355 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
356 #define CONFIG_BOOTFILE "uImage"
358 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
360 #define CONFIG_PREBOOT "echo;" \
361 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
364 #define CONFIG_EXTRA_ENV_SETTINGS \
366 "hostname=mpc8349emds\0" \
367 "nfsargs=setenv bootargs root=/dev/nfs rw " \
368 "nfsroot=${serverip}:${rootpath}\0" \
369 "ramargs=setenv bootargs root=/dev/ram rw\0" \
370 "addip=setenv bootargs ${bootargs} " \
371 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
372 ":${hostname}:${netdev}:off panic=1\0" \
373 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
374 "flash_nfs=run nfsargs addip addtty;" \
375 "bootm ${kernel_addr}\0" \
376 "flash_self=run ramargs addip addtty;" \
377 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
378 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
380 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
381 "update=protect off fe000000 fe03ffff; " \
382 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
383 "upd=run load update\0" \
385 "fdtfile=mpc834x_mds.dtb\0" \
388 #define CONFIG_NFSBOOTCOMMAND \
389 "setenv bootargs root=/dev/nfs rw " \
390 "nfsroot=$serverip:$rootpath " \
391 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
393 "console=$consoledev,$baudrate $othbootargs;" \
394 "tftp $loadaddr $bootfile;" \
395 "tftp $fdtaddr $fdtfile;" \
396 "bootm $loadaddr - $fdtaddr"
398 #define CONFIG_RAMBOOTCOMMAND \
399 "setenv bootargs root=/dev/ram rw " \
400 "console=$consoledev,$baudrate $othbootargs;" \
401 "tftp $ramdiskaddr $ramdiskfile;" \
402 "tftp $loadaddr $bootfile;" \
403 "tftp $fdtaddr $fdtfile;" \
404 "bootm $loadaddr $ramdiskaddr $fdtaddr"
406 #define CONFIG_BOOTCOMMAND "run flash_self"
408 #endif /* __CONFIG_H */