sunxi: Add support for using MII phy-s with the GMAC nic
[oweals/u-boot.git] / include / configs / MPC832XEMDS.h
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * High Level Configuration Options
12  */
13 #define CONFIG_E300             1       /* E300 family */
14 #define CONFIG_QE               1       /* Has QE */
15 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
16 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
17
18 #define CONFIG_SYS_TEXT_BASE    0xFE000000
19
20 /*
21  * System Clock Setup
22  */
23 #ifdef CONFIG_PCISLAVE
24 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
25 #else
26 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
27 #endif
28
29 #ifndef CONFIG_SYS_CLK_FREQ
30 #define CONFIG_SYS_CLK_FREQ     66000000
31 #endif
32
33 /*
34  * Hardware Reset Configuration Word
35  */
36 #define CONFIG_SYS_HRCW_LOW (\
37         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38         HRCWL_DDR_TO_SCB_CLK_2X1 |\
39         HRCWL_VCO_1X2 |\
40         HRCWL_CSB_TO_CLKIN_2X1 |\
41         HRCWL_CORE_TO_CSB_2X1 |\
42         HRCWL_CE_PLL_VCO_DIV_2 |\
43         HRCWL_CE_PLL_DIV_1X1 |\
44         HRCWL_CE_TO_PLL_1X3)
45
46 #ifdef CONFIG_PCISLAVE
47 #define CONFIG_SYS_HRCW_HIGH (\
48         HRCWH_PCI_AGENT |\
49         HRCWH_PCI1_ARBITER_DISABLE |\
50         HRCWH_CORE_ENABLE |\
51         HRCWH_FROM_0XFFF00100 |\
52         HRCWH_BOOTSEQ_DISABLE |\
53         HRCWH_SW_WATCHDOG_DISABLE |\
54         HRCWH_ROM_LOC_LOCAL_16BIT |\
55         HRCWH_BIG_ENDIAN |\
56         HRCWH_LALE_NORMAL)
57 #else
58 #define CONFIG_SYS_HRCW_HIGH (\
59         HRCWH_PCI_HOST |\
60         HRCWH_PCI1_ARBITER_ENABLE |\
61         HRCWH_CORE_ENABLE |\
62         HRCWH_FROM_0X00000100 |\
63         HRCWH_BOOTSEQ_DISABLE |\
64         HRCWH_SW_WATCHDOG_DISABLE |\
65         HRCWH_ROM_LOC_LOCAL_16BIT |\
66         HRCWH_BIG_ENDIAN |\
67         HRCWH_LALE_NORMAL)
68 #endif
69
70 /*
71  * System IO Config
72  */
73 #define CONFIG_SYS_SICRL                0x00000000
74
75 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
76 #define CONFIG_BOARD_EARLY_INIT_R
77
78 /*
79  * IMMR new address
80  */
81 #define CONFIG_SYS_IMMR         0xE0000000
82
83 /*
84  * DDR Setup
85  */
86 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
87 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
88 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
89 #define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
90
91 #undef CONFIG_SPD_EEPROM
92 #if defined(CONFIG_SPD_EEPROM)
93 /* Determine DDR configuration from I2C interface
94  */
95 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
96 #else
97 /* Manually set up DDR parameters
98  */
99 #define CONFIG_SYS_DDR_SIZE             128     /* MB */
100 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
101                                         | CSCONFIG_AP \
102                                         | CSCONFIG_ODT_WR_CFG \
103                                         | CSCONFIG_ROW_BIT_13 \
104                                         | CSCONFIG_COL_BIT_10)
105                                         /* 0x80840102 */
106 #define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
107                                         | (0 << TIMING_CFG0_WRT_SHIFT) \
108                                         | (0 << TIMING_CFG0_RRT_SHIFT) \
109                                         | (0 << TIMING_CFG0_WWT_SHIFT) \
110                                         | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
111                                         | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
112                                         | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
113                                         | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
114                                         /* 0x00220802 */
115 #define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
116                                         | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
117                                         | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
118                                         | (5 << TIMING_CFG1_CASLAT_SHIFT) \
119                                         | (13 << TIMING_CFG1_REFREC_SHIFT) \
120                                         | (3 << TIMING_CFG1_WRREC_SHIFT) \
121                                         | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
122                                         | (2 << TIMING_CFG1_WRTORD_SHIFT))
123                                         /* 0x3935D322 */
124 #define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
125                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
126                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
127                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
128                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
129                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
130                                 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
131                                 /* 0x0F9048CA */
132 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
133 #define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
134                                         /* 0x02000000 */
135 #define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
136                                         | (0x0232 << SDRAM_MODE_SD_SHIFT))
137                                         /* 0x44400232 */
138 #define CONFIG_SYS_DDR_MODE2            0x8000c000
139 #define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
140                                         | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
141                                         /* 0x03200064 */
142 #define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
143 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
144                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
145                                         | SDRAM_CFG_32_BE)
146                                         /* 0x43080000 */
147 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
148 #endif
149
150 /*
151  * Memory test
152  */
153 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
154 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
155 #define CONFIG_SYS_MEMTEST_END          0x00100000
156
157 /*
158  * The reserved memory
159  */
160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
161
162 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
163 #define CONFIG_SYS_RAMBOOT
164 #else
165 #undef  CONFIG_SYS_RAMBOOT
166 #endif
167
168 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
169 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
170 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
171
172 /*
173  * Initial RAM Base Address Setup
174  */
175 #define CONFIG_SYS_INIT_RAM_LOCK        1
176 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
177 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
178 #define CONFIG_SYS_GBL_DATA_OFFSET      \
179                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180
181 /*
182  * Local Bus Configuration & Clock Setup
183  */
184 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
185 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
186 #define CONFIG_SYS_LBC_LBCR             0x00000000
187
188 /*
189  * FLASH on the Local Bus
190  */
191 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
192 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
193 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
194 #define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
195 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
196
197                                         /* Window base at flash base */
198 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
199 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
200
201 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
202                                 | BR_PS_16      /* 16 bit port */ \
203                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
204                                 | BR_V)         /* valid */
205 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
206                                 | OR_GPCM_XAM \
207                                 | OR_GPCM_CSNT \
208                                 | OR_GPCM_ACS_DIV2 \
209                                 | OR_GPCM_XACS \
210                                 | OR_GPCM_SCY_15 \
211                                 | OR_GPCM_TRLX_SET \
212                                 | OR_GPCM_EHTR_SET \
213                                 | OR_GPCM_EAD)
214                                 /* 0xfe006ff7 */
215
216 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
218
219 #undef CONFIG_SYS_FLASH_CHECKSUM
220
221 /*
222  * BCSR on the Local Bus
223  */
224 #define CONFIG_SYS_BCSR                 0xF8000000
225                                         /* Access window base at BCSR base */
226 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
227 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
228
229 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
230                                         | BR_PS_8 \
231                                         | BR_MS_GPCM \
232                                         | BR_V)
233 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
234                                         | OR_GPCM_XAM \
235                                         | OR_GPCM_CSNT \
236                                         | OR_GPCM_XACS \
237                                         | OR_GPCM_SCY_15 \
238                                         | OR_GPCM_TRLX_SET \
239                                         | OR_GPCM_EHTR_SET \
240                                         | OR_GPCM_EAD)
241                                         /* 0xFFFFE9F7 */
242
243 /*
244  * Windows to access PIB via local bus
245  */
246                                         /* PIB window base 0xF8008000 */
247 #define CONFIG_SYS_PIB_BASE             0xF8008000
248 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
249 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PIB_BASE
250 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
251
252 /*
253  * CS2 on Local Bus, to PIB
254  */
255 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_PIB_BASE \
256                                 | BR_PS_8 \
257                                 | BR_MS_GPCM \
258                                 | BR_V)
259                                 /* 0xF8008801 */
260 #define CONFIG_SYS_OR2_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
261                                 | OR_GPCM_XAM \
262                                 | OR_GPCM_CSNT \
263                                 | OR_GPCM_XACS \
264                                 | OR_GPCM_SCY_15 \
265                                 | OR_GPCM_TRLX_SET \
266                                 | OR_GPCM_EHTR_SET \
267                                 | OR_GPCM_EAD)
268                                 /* 0xffffe9f7 */
269
270 /*
271  * CS3 on Local Bus, to PIB
272  */
273 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIB_BASE + \
274                                         CONFIG_SYS_PIB_WINDOW_SIZE) \
275                                 | BR_PS_8 \
276                                 | BR_MS_GPCM \
277                                 | BR_V)
278                                 /* 0xF8010801 */
279 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
280                                 | OR_GPCM_XAM \
281                                 | OR_GPCM_CSNT \
282                                 | OR_GPCM_XACS \
283                                 | OR_GPCM_SCY_15 \
284                                 | OR_GPCM_TRLX_SET \
285                                 | OR_GPCM_EHTR_SET \
286                                 | OR_GPCM_EAD)
287                                 /* 0xffffe9f7 */
288
289 /*
290  * Serial Port
291  */
292 #define CONFIG_CONS_INDEX       1
293 #define CONFIG_SYS_NS16550
294 #define CONFIG_SYS_NS16550_SERIAL
295 #define CONFIG_SYS_NS16550_REG_SIZE     1
296 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
297
298 #define CONFIG_SYS_BAUDRATE_TABLE  \
299                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
300
301 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
302 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
303
304 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
305 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
306 /* Use the HUSH parser */
307 #define CONFIG_SYS_HUSH_PARSER
308
309 /* pass open firmware flat tree */
310 #define CONFIG_OF_LIBFDT        1
311 #define CONFIG_OF_BOARD_SETUP   1
312 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
313
314 /* I2C */
315 #define CONFIG_SYS_I2C
316 #define CONFIG_SYS_I2C_FSL
317 #define CONFIG_SYS_FSL_I2C_SPEED        400000
318 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
319 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
320 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
321
322 /*
323  * Config on-board RTC
324  */
325 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
326 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
327
328 /*
329  * General PCI
330  * Addresses are mapped 1-1.
331  */
332 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
333 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
334 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
335 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
336 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
337 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
338 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
339 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
340 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
341
342 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
343 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
344 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
345
346
347 #ifdef CONFIG_PCI
348 #define CONFIG_PCI_INDIRECT_BRIDGE
349
350 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
351 #define CONFIG_83XX_PCI_STREAMING
352
353 #undef CONFIG_EEPRO100
354 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
355 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
356
357 #endif  /* CONFIG_PCI */
358
359 /*
360  * QE UEC ethernet configuration
361  */
362 #define CONFIG_UEC_ETH
363 #define CONFIG_ETHPRIME         "UEC0"
364
365 #define CONFIG_UEC_ETH1         /* ETH3 */
366
367 #ifdef CONFIG_UEC_ETH1
368 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
369 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
370 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
371 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
372 #define CONFIG_SYS_UEC1_PHY_ADDR        3
373 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
374 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
375 #endif
376
377 #define CONFIG_UEC_ETH2         /* ETH4 */
378
379 #ifdef CONFIG_UEC_ETH2
380 #define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
381 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
382 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
383 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
384 #define CONFIG_SYS_UEC2_PHY_ADDR        4
385 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
386 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
387 #endif
388
389 /*
390  * Environment
391  */
392 #ifndef CONFIG_SYS_RAMBOOT
393         #define CONFIG_ENV_IS_IN_FLASH  1
394         #define CONFIG_ENV_ADDR         \
395                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
396         #define CONFIG_ENV_SECT_SIZE    0x20000
397         #define CONFIG_ENV_SIZE         0x2000
398 #else
399         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
400         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
401         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
402         #define CONFIG_ENV_SIZE         0x2000
403 #endif
404
405 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
406 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
407
408 /*
409  * BOOTP options
410  */
411 #define CONFIG_BOOTP_BOOTFILESIZE
412 #define CONFIG_BOOTP_BOOTPATH
413 #define CONFIG_BOOTP_GATEWAY
414 #define CONFIG_BOOTP_HOSTNAME
415
416
417 /*
418  * Command line configuration.
419  */
420 #include <config_cmd_default.h>
421
422 #define CONFIG_CMD_PING
423 #define CONFIG_CMD_I2C
424 #define CONFIG_CMD_ASKENV
425
426 #if defined(CONFIG_PCI)
427     #define CONFIG_CMD_PCI
428 #endif
429
430 #if defined(CONFIG_SYS_RAMBOOT)
431     #undef CONFIG_CMD_SAVEENV
432     #undef CONFIG_CMD_LOADS
433 #endif
434
435
436 #undef CONFIG_WATCHDOG          /* watchdog disabled */
437
438 /*
439  * Miscellaneous configurable options
440  */
441 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
442 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
443
444 #if defined(CONFIG_CMD_KGDB)
445         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
446 #else
447         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
448 #endif
449
450                                 /* Print Buffer Size */
451 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
452 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
453                                 /* Boot Argument Buffer Size */
454 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
455
456 /*
457  * For booting Linux, the board info and command line data
458  * have to be in the first 256 MB of memory, since this is
459  * the maximum mapped by the Linux kernel during initialization.
460  */
461                                         /* Initial Memory map for Linux */
462 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
463
464 /*
465  * Core HID Setup
466  */
467 #define CONFIG_SYS_HID0_INIT    0x000000000
468 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
469                                  HID0_ENABLE_INSTRUCTION_CACHE)
470 #define CONFIG_SYS_HID2         HID2_HBE
471
472 /*
473  * MMU Setup
474  */
475
476 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
477
478 /* DDR: cache cacheable */
479 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
480                                 | BATL_PP_RW \
481                                 | BATL_MEMCOHERENCE)
482 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
483                                 | BATU_BL_256M \
484                                 | BATU_VS \
485                                 | BATU_VP)
486 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
487 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
488
489 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
490 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
491                                 | BATL_PP_RW \
492                                 | BATL_CACHEINHIBIT \
493                                 | BATL_GUARDEDSTORAGE)
494 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
495                                 | BATU_BL_4M \
496                                 | BATU_VS \
497                                 | BATU_VP)
498 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
499 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
500
501 /* BCSR: cache-inhibit and guarded */
502 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
503                                 | BATL_PP_RW \
504                                 | BATL_CACHEINHIBIT \
505                                 | BATL_GUARDEDSTORAGE)
506 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
507                                 | BATU_BL_128K \
508                                 | BATU_VS \
509                                 | BATU_VP)
510 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
511 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
512
513 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
514 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
515                                 | BATL_PP_RW \
516                                 | BATL_MEMCOHERENCE)
517 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
518                                 | BATU_BL_32M \
519                                 | BATU_VS \
520                                 | BATU_VP)
521 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
522                                 | BATL_PP_RW \
523                                 | BATL_CACHEINHIBIT \
524                                 | BATL_GUARDEDSTORAGE)
525 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
526
527 #define CONFIG_SYS_IBAT4L       (0)
528 #define CONFIG_SYS_IBAT4U       (0)
529 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
530 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
531
532 /* Stack in dcache: cacheable, no memory coherence */
533 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
534 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
535                                 | BATU_BL_128K \
536                                 | BATU_VS \
537                                 | BATU_VP)
538 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
539 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
540
541 #ifdef CONFIG_PCI
542 /* PCI MEM space: cacheable */
543 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
544                                 | BATL_PP_RW \
545                                 | BATL_MEMCOHERENCE)
546 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
547                                 | BATU_BL_256M \
548                                 | BATU_VS \
549                                 | BATU_VP)
550 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
551 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
552 /* PCI MMIO space: cache-inhibit and guarded */
553 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
554                                 | BATL_PP_RW \
555                                 | BATL_CACHEINHIBIT \
556                                 | BATL_GUARDEDSTORAGE)
557 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
558                                 | BATU_BL_256M \
559                                 | BATU_VS \
560                                 | BATU_VP)
561 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
562 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
563 #else
564 #define CONFIG_SYS_IBAT6L       (0)
565 #define CONFIG_SYS_IBAT6U       (0)
566 #define CONFIG_SYS_IBAT7L       (0)
567 #define CONFIG_SYS_IBAT7U       (0)
568 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
569 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
570 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
571 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
572 #endif
573
574 #if defined(CONFIG_CMD_KGDB)
575 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
576 #endif
577
578 /*
579  * Environment Configuration
580  */ #define CONFIG_ENV_OVERWRITE
581
582 #if defined(CONFIG_UEC_ETH)
583 #define CONFIG_HAS_ETH0
584 #define CONFIG_HAS_ETH1
585 #endif
586
587 #define CONFIG_BAUDRATE 115200
588
589 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
590
591 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
592 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
593
594 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
595         "netdev=eth0\0"                                                 \
596         "consoledev=ttyS0\0"                                            \
597         "ramdiskaddr=1000000\0"                                         \
598         "ramdiskfile=ramfs.83xx\0"                                      \
599         "fdtaddr=780000\0"                                              \
600         "fdtfile=mpc832x_mds.dtb\0"                                     \
601         ""
602
603 #define CONFIG_NFSBOOTCOMMAND                                           \
604         "setenv bootargs root=/dev/nfs rw "                             \
605                 "nfsroot=$serverip:$rootpath "                          \
606                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
607                                                         "$netdev:off "  \
608                 "console=$consoledev,$baudrate $othbootargs;"           \
609         "tftp $loadaddr $bootfile;"                                     \
610         "tftp $fdtaddr $fdtfile;"                                       \
611         "bootm $loadaddr - $fdtaddr"
612
613 #define CONFIG_RAMBOOTCOMMAND                                           \
614         "setenv bootargs root=/dev/ram rw "                             \
615                 "console=$consoledev,$baudrate $othbootargs;"           \
616         "tftp $ramdiskaddr $ramdiskfile;"                               \
617         "tftp $loadaddr $bootfile;"                                     \
618         "tftp $fdtaddr $fdtfile;"                                       \
619         "bootm $loadaddr $ramdiskaddr $fdtaddr"
620
621
622 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
623
624 #endif  /* __CONFIG_H */