2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
21 #define CONFIG_SYS_SICRL 0x00000000
26 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
27 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
28 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
30 #undef CONFIG_SPD_EEPROM
31 #if defined(CONFIG_SPD_EEPROM)
32 /* Determine DDR configuration from I2C interface
34 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
36 /* Manually set up DDR parameters
38 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
39 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
40 | CSCONFIG_ROW_BIT_13 \
43 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
44 | (0 << TIMING_CFG0_WRT_SHIFT) \
45 | (0 << TIMING_CFG0_RRT_SHIFT) \
46 | (0 << TIMING_CFG0_WWT_SHIFT) \
47 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
48 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
49 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
50 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
52 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
53 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
54 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
55 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
56 | (3 << TIMING_CFG1_REFREC_SHIFT) \
57 | (2 << TIMING_CFG1_WRREC_SHIFT) \
58 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
59 | (2 << TIMING_CFG1_WRTORD_SHIFT))
61 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
62 | (31 << TIMING_CFG2_CPO_SHIFT) \
63 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
64 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
65 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
66 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
67 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
70 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
72 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
73 | (0x0232 << SDRAM_MODE_SD_SHIFT))
75 #define CONFIG_SYS_DDR_MODE2 0x8000c000
76 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
77 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
79 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
80 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
81 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
84 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
90 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
91 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
92 #define CONFIG_SYS_MEMTEST_END 0x03f00000
97 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
99 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
100 #define CONFIG_SYS_RAMBOOT
102 #undef CONFIG_SYS_RAMBOOT
105 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
106 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
107 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
110 * Initial RAM Base Address Setup
112 #define CONFIG_SYS_INIT_RAM_LOCK 1
113 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
114 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
115 #define CONFIG_SYS_GBL_DATA_OFFSET \
116 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
119 * Local Bus Configuration & Clock Setup
121 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
122 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
123 #define CONFIG_SYS_LBC_LBCR 0x00000000
126 * FLASH on the Local Bus
128 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
129 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
136 #undef CONFIG_SYS_FLASH_CHECKSUM
141 #define CONFIG_SYS_NS16550_SERIAL
142 #define CONFIG_SYS_NS16550_REG_SIZE 1
143 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
145 #define CONFIG_SYS_BAUDRATE_TABLE \
146 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
148 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
149 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
152 #define CONFIG_SYS_I2C
153 #define CONFIG_SYS_I2C_FSL
154 #define CONFIG_SYS_FSL_I2C_SPEED 400000
155 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
156 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
157 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
160 * Config on-board EEPROM
162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
164 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
165 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
169 * Addresses are mapped 1-1.
171 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
172 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
173 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
174 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
175 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
176 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
177 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
178 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
179 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
182 #define CONFIG_PCI_INDIRECT_BRIDGE
183 #define CONFIG_PCI_SKIP_HOST_BRIDGE
185 #undef CONFIG_EEPRO100
186 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
187 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
189 #endif /* CONFIG_PCI */
192 * QE UEC ethernet configuration
194 #define CONFIG_UEC_ETH
195 #define CONFIG_ETHPRIME "UEC0"
197 #define CONFIG_UEC_ETH1 /* ETH3 */
199 #ifdef CONFIG_UEC_ETH1
200 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
201 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
202 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
203 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
204 #define CONFIG_SYS_UEC1_PHY_ADDR 4
205 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
206 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
209 #define CONFIG_UEC_ETH2 /* ETH4 */
211 #ifdef CONFIG_UEC_ETH2
212 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
213 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
214 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
215 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
216 #define CONFIG_SYS_UEC2_PHY_ADDR 0
217 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
218 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
224 #ifndef CONFIG_SYS_RAMBOOT
225 #define CONFIG_ENV_ADDR \
226 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
227 #define CONFIG_ENV_SECT_SIZE 0x20000
228 #define CONFIG_ENV_SIZE 0x2000
230 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
231 #define CONFIG_ENV_SIZE 0x2000
234 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
235 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
240 #define CONFIG_BOOTP_BOOTFILESIZE
243 * Command line configuration.
246 #undef CONFIG_WATCHDOG /* watchdog disabled */
249 * Miscellaneous configurable options
251 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
254 * For booting Linux, the board info and command line data
255 * have to be in the first 256 MB of memory, since this is
256 * the maximum mapped by the Linux kernel during initialization.
258 /* Initial Memory map for Linux */
259 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
260 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
262 #if (CONFIG_CMD_KGDB)
263 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
267 * Environment Configuration
269 #define CONFIG_ENV_OVERWRITE
271 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
272 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
274 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
275 * (see CONFIG_SYS_I2C_EEPROM) */
276 /* MAC address offset in I2C EEPROM */
277 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
279 #define CONFIG_NETDEV "eth1"
281 #define CONFIG_HOSTNAME "mpc8323erdb"
282 #define CONFIG_ROOTPATH "/nfsroot"
283 #define CONFIG_BOOTFILE "uImage"
284 /* U-Boot image on TFTP server */
285 #define CONFIG_UBOOTPATH "u-boot.bin"
286 #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
287 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
289 /* default location for tftp and bootm */
290 #define CONFIG_LOADADDR 800000
292 #define CONFIG_EXTRA_ENV_SETTINGS \
293 "netdev=" CONFIG_NETDEV "\0" \
294 "uboot=" CONFIG_UBOOTPATH "\0" \
295 "tftpflash=tftp $loadaddr $uboot;" \
296 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
298 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
300 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
302 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
304 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
307 "fdtfile=" CONFIG_FDTFILE "\0" \
308 "ramdiskaddr=1000000\0" \
309 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
311 "setbootargs=setenv bootargs " \
312 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
313 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
314 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
316 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
318 #define CONFIG_NFSBOOTCOMMAND \
319 "setenv rootdev /dev/nfs;" \
322 "tftp $loadaddr $bootfile;" \
323 "tftp $fdtaddr $fdtfile;" \
324 "bootm $loadaddr - $fdtaddr"
326 #define CONFIG_RAMBOOTCOMMAND \
327 "setenv rootdev /dev/ram;" \
329 "tftp $ramdiskaddr $ramdiskfile;" \
330 "tftp $loadaddr $bootfile;" \
331 "tftp $fdtaddr $fdtfile;" \
332 "bootm $loadaddr $ramdiskaddr $fdtaddr"
334 #endif /* __CONFIG_H */