include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * Hardware Reset Configuration Word
  20  */
  21 #define CONFIG_SYS_HRCW_LOW (\
  22         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  23         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  24         HRCWL_VCO_1X2 |\
  25         HRCWL_CSB_TO_CLKIN_2X1 |\
  26         HRCWL_CORE_TO_CSB_2_5X1 |\
  27         HRCWL_CE_PLL_VCO_DIV_2 |\
  28         HRCWL_CE_PLL_DIV_1X1 |\
  29         HRCWL_CE_TO_PLL_1X3)
  30
  31 #define CONFIG_SYS_HRCW_HIGH (\
  32         HRCWH_PCI_HOST |\
  33         HRCWH_PCI1_ARBITER_ENABLE |\
  34         HRCWH_CORE_ENABLE |\
  35         HRCWH_FROM_0X00000100 |\
  36         HRCWH_BOOTSEQ_DISABLE |\
  37         HRCWH_SW_WATCHDOG_DISABLE |\
  38         HRCWH_ROM_LOC_LOCAL_16BIT |\
  39         HRCWH_BIG_ENDIAN |\
  40         HRCWH_LALE_NORMAL)
  41
  42 /*
  43  * System IO Config
  44  */
  45 #define CONFIG_SYS_SICRL                0x00000000
  46
  47 /*
  48  * IMMR new address
  49  */
  50 #define CONFIG_SYS_IMMR         0xE0000000
  51
  52 /*
  53  * System performance
  54  */
  55 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  56 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  57 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  58 #define CONFIG_SYS_SPCR_OPT     1
  59
  60 /*
  61  * DDR Setup
  62  */
  63 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  64 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66
  67 #undef CONFIG_SPD_EEPROM
  68 #if defined(CONFIG_SPD_EEPROM)
  69 /* Determine DDR configuration from I2C interface
  70  */
  71 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  72 #else
  73 /* Manually set up DDR parameters
  74  */
  75 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  76 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  77                                 | CSCONFIG_ROW_BIT_13 \
  78                                 | CSCONFIG_COL_BIT_9)
  79                                 /* 0x80010101 */
  80 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  81                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  82                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  83                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  84                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  85                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  86                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  87                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  88                                 /* 0x00220802 */
  89 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  90                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  91                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  92                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  93                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  94                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  95                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  96                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  97                                 /* 0x26253222 */
  98 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  99                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 100                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 101                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 102                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 103                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 104                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 105                                 /* 0x1f9048c7 */
 106 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 107 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 108                                 /* 0x02000000 */
 109 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 110                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 111                                 /* 0x44480232 */
 112 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 113 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 114                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 115                                 /* 0x03200064 */
 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 117 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 118                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 119                                 | SDRAM_CFG_32_BE)
 120                                 /* 0x43080000 */
 121 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 122 #endif
 123
 124 /*
 125  * Memory test
 126  */
 127 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 128 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 129 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 130
 131 /*
 132  * The reserved memory
 133  */
 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 135
 136 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 137 #define CONFIG_SYS_RAMBOOT
 138 #else
 139 #undef  CONFIG_SYS_RAMBOOT
 140 #endif
 141
 142 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 143 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 144 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 145
 146 /*
 147  * Initial RAM Base Address Setup
 148  */
 149 #define CONFIG_SYS_INIT_RAM_LOCK        1
 150 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 151 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 152 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 153                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 154
 155 /*
 156  * Local Bus Configuration & Clock Setup
 157  */
 158 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 159 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 160 #define CONFIG_SYS_LBC_LBCR             0x00000000
 161
 162 /*
 163  * FLASH on the Local Bus
 164  */
 165 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 166 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 167
 168                                         /* Window base at flash base */
 169 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 170 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 171
 172 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 173                                 | BR_PS_16      /* 16 bit port */ \
 174                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 175                                 | BR_V)         /* valid */
 176 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 177                                 | OR_GPCM_XAM \
 178                                 | OR_GPCM_CSNT \
 179                                 | OR_GPCM_ACS_DIV2 \
 180                                 | OR_GPCM_XACS \
 181                                 | OR_GPCM_SCY_15 \
 182                                 | OR_GPCM_TRLX_SET \
 183                                 | OR_GPCM_EHTR_SET \
 184                                 | OR_GPCM_EAD)
 185                                 /* 0xFE006FF7 */
 186
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 188 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 189
 190 #undef CONFIG_SYS_FLASH_CHECKSUM
 191
 192 /*
 193  * Serial Port
 194  */
 195 #define CONFIG_SYS_NS16550_SERIAL
 196 #define CONFIG_SYS_NS16550_REG_SIZE     1
 197 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 198
 199 #define CONFIG_SYS_BAUDRATE_TABLE  \
 200                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 201
 202 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 203 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 204
 205 /* I2C */
 206 #define CONFIG_SYS_I2C
 207 #define CONFIG_SYS_I2C_FSL
 208 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 209 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 210 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 211 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 212
 213 /*
 214  * Config on-board EEPROM
 215  */
 216 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 220
 221 /*
 222  * General PCI
 223  * Addresses are mapped 1-1.
 224  */
 225 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 226 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 227 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 228 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 229 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 230 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 231 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 232 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 233 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 234
 235 #ifdef CONFIG_PCI
 236 #define CONFIG_PCI_INDIRECT_BRIDGE
 237 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 238
 239 #undef CONFIG_EEPRO100
 240 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 241 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 242
 243 #endif  /* CONFIG_PCI */
 244
 245 /*
 246  * QE UEC ethernet configuration
 247  */
 248 #define CONFIG_UEC_ETH
 249 #define CONFIG_ETHPRIME         "UEC0"
 250
 251 #define CONFIG_UEC_ETH1         /* ETH3 */
 252
 253 #ifdef CONFIG_UEC_ETH1
 254 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 255 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 256 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 257 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 258 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 259 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 260 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 261 #endif
 262
 263 #define CONFIG_UEC_ETH2         /* ETH4 */
 264
 265 #ifdef CONFIG_UEC_ETH2
 266 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 267 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 268 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 269 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 270 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 271 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 272 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 273 #endif
 274
 275 /*
 276  * Environment
 277  */
 278 #ifndef CONFIG_SYS_RAMBOOT
 279         #define CONFIG_ENV_ADDR         \
 280                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 281         #define CONFIG_ENV_SECT_SIZE    0x20000
 282         #define CONFIG_ENV_SIZE         0x2000
 283 #else
 284         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 285         #define CONFIG_ENV_SIZE         0x2000
 286 #endif
 287
 288 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 289 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 290
 291 /*
 292  * BOOTP options
 293  */
 294 #define CONFIG_BOOTP_BOOTFILESIZE
 295
 296 /*
 297  * Command line configuration.
 298  */
 299
 300 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 301
 302 /*
 303  * Miscellaneous configurable options
 304  */
 305 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 306
 307 /*
 308  * For booting Linux, the board info and command line data
 309  * have to be in the first 256 MB of memory, since this is
 310  * the maximum mapped by the Linux kernel during initialization.
 311  */
 312                                         /* Initial Memory map for Linux */
 313 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 314 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 315
 316 /*
 317  * Core HID Setup
 318  */
 319 #define CONFIG_SYS_HID0_INIT    0x000000000
 320 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 321                                  HID0_ENABLE_INSTRUCTION_CACHE)
 322 #define CONFIG_SYS_HID2         HID2_HBE
 323
 324 /*
 325  * MMU Setup
 326  */
 327 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 328
 329 /* DDR: cache cacheable */
 330 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 331                                 | BATL_PP_RW \
 332                                 | BATL_MEMCOHERENCE)
 333 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 334                                 | BATU_BL_256M \
 335                                 | BATU_VS \
 336                                 | BATU_VP)
 337 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 338 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 339
 340 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 341 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 342                                 | BATL_PP_RW \
 343                                 | BATL_CACHEINHIBIT \
 344                                 | BATL_GUARDEDSTORAGE)
 345 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 346                                 | BATU_BL_4M \
 347                                 | BATU_VS \
 348                                 | BATU_VP)
 349 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 350 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 351
 352 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 353 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 354                                 | BATL_PP_RW \
 355                                 | BATL_MEMCOHERENCE)
 356 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 357                                 | BATU_BL_32M \
 358                                 | BATU_VS \
 359                                 | BATU_VP)
 360 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 361                                 | BATL_PP_RW \
 362                                 | BATL_CACHEINHIBIT \
 363                                 | BATL_GUARDEDSTORAGE)
 364 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 365
 366 #define CONFIG_SYS_IBAT3L       (0)
 367 #define CONFIG_SYS_IBAT3U       (0)
 368 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 369 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 370
 371 /* Stack in dcache: cacheable, no memory coherence */
 372 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 373 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 374                                 | BATU_BL_128K \
 375                                 | BATU_VS \
 376                                 | BATU_VP)
 377 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 378 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 379
 380 #ifdef CONFIG_PCI
 381 /* PCI MEM space: cacheable */
 382 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 383                                 | BATL_PP_RW \
 384                                 | BATL_MEMCOHERENCE)
 385 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 386                                 | BATU_BL_256M \
 387                                 | BATU_VS \
 388                                 | BATU_VP)
 389 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 390 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 391 /* PCI MMIO space: cache-inhibit and guarded */
 392 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 393                                 | BATL_PP_RW \
 394                                 | BATL_CACHEINHIBIT \
 395                                 | BATL_GUARDEDSTORAGE)
 396 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 397                                 | BATU_BL_256M \
 398                                 | BATU_VS \
 399                                 | BATU_VP)
 400 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 401 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 402 #else
 403 #define CONFIG_SYS_IBAT5L       (0)
 404 #define CONFIG_SYS_IBAT5U       (0)
 405 #define CONFIG_SYS_IBAT6L       (0)
 406 #define CONFIG_SYS_IBAT6U       (0)
 407 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 408 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 409 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 410 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 411 #endif
 412
 413 /* Nothing in BAT7 */
 414 #define CONFIG_SYS_IBAT7L       (0)
 415 #define CONFIG_SYS_IBAT7U       (0)
 416 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 417 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 418
 419 #if (CONFIG_CMD_KGDB)
 420 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 421 #endif
 422
 423 /*
 424  * Environment Configuration
 425  */
 426 #define CONFIG_ENV_OVERWRITE
 427
 428 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 429 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 430
 431 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 432  * (see CONFIG_SYS_I2C_EEPROM) */
 433                                         /* MAC address offset in I2C EEPROM */
 434 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 435
 436 #define CONFIG_NETDEV           "eth1"
 437
 438 #define CONFIG_HOSTNAME         "mpc8323erdb"
 439 #define CONFIG_ROOTPATH         "/nfsroot"
 440 #define CONFIG_BOOTFILE         "uImage"
 441                                 /* U-Boot image on TFTP server */
 442 #define CONFIG_UBOOTPATH        "u-boot.bin"
 443 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 444 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 445
 446                                 /* default location for tftp and bootm */
 447 #define CONFIG_LOADADDR         800000
 448
 449 #define CONFIG_EXTRA_ENV_SETTINGS \
 450         "netdev=" CONFIG_NETDEV "\0"                                    \
 451         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 452         "tftpflash=tftp $loadaddr $uboot;"                              \
 453                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 454                         " +$filesize; " \
 455                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 456                         " +$filesize; " \
 457                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 458                         " $filesize; "  \
 459                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 460                         " +$filesize; " \
 461                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 462                         " $filesize\0"  \
 463         "fdtaddr=780000\0"                                              \
 464         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 465         "ramdiskaddr=1000000\0"                                         \
 466         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 467         "console=ttyS0\0"                                               \
 468         "setbootargs=setenv bootargs "                                  \
 469                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 470         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 471                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 472                                                                 "$netdev:off "\
 473                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 474
 475 #define CONFIG_NFSBOOTCOMMAND                                           \
 476         "setenv rootdev /dev/nfs;"                                      \
 477         "run setbootargs;"                                              \
 478         "run setipargs;"                                                \
 479         "tftp $loadaddr $bootfile;"                                     \
 480         "tftp $fdtaddr $fdtfile;"                                       \
 481         "bootm $loadaddr - $fdtaddr"
 482
 483 #define CONFIG_RAMBOOTCOMMAND                                           \
 484         "setenv rootdev /dev/ram;"                                      \
 485         "run setbootargs;"                                              \
 486         "tftp $ramdiskaddr $ramdiskfile;"                               \
 487         "tftp $loadaddr $bootfile;"                                     \
 488         "tftp $fdtaddr $fdtfile;"                                       \
 489         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 490
 491 #endif  /* __CONFIG_H */