2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
17 #define CONFIG_MPC83xx 1 /* MPC83xx family */
18 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
25 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
27 #ifndef CONFIG_SYS_CLK_FREQ
28 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
32 * Hardware Reset Configuration Word
34 #define CONFIG_SYS_HRCW_LOW (\
35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
36 HRCWL_DDR_TO_SCB_CLK_2X1 |\
38 HRCWL_CSB_TO_CLKIN_2X1 |\
39 HRCWL_CORE_TO_CSB_2_5X1 |\
40 HRCWL_CE_PLL_VCO_DIV_2 |\
41 HRCWL_CE_PLL_DIV_1X1 |\
44 #define CONFIG_SYS_HRCW_HIGH (\
46 HRCWH_PCI1_ARBITER_ENABLE |\
48 HRCWH_FROM_0X00000100 |\
49 HRCWH_BOOTSEQ_DISABLE |\
50 HRCWH_SW_WATCHDOG_DISABLE |\
51 HRCWH_ROM_LOC_LOCAL_16BIT |\
58 #define CONFIG_SYS_SICRL 0x00000000
60 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
65 #define CONFIG_SYS_IMMR 0xE0000000
70 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
71 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
72 #define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
77 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
79 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
80 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
82 #undef CONFIG_SPD_EEPROM
83 #if defined(CONFIG_SPD_EEPROM)
84 /* Determine DDR configuration from I2C interface
86 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
88 /* Manually set up DDR parameters
90 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
91 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
92 | CSCONFIG_ODT_WR_ACS \
93 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
95 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
96 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
97 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
98 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
99 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
100 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
101 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
102 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
104 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
105 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
106 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
107 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
108 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
109 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
110 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
111 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
113 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
114 | (31 << TIMING_CFG2_CPO_SHIFT ) \
115 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
116 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
117 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
118 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
119 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
121 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
122 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124 #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
125 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
127 #define CONFIG_SYS_DDR_MODE2 0x8000c000
128 #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
129 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
131 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
132 #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
136 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
142 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
143 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
144 #define CONFIG_SYS_MEMTEST_END 0x03f00000
147 * The reserved memory
149 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
151 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
152 #define CONFIG_SYS_RAMBOOT
154 #undef CONFIG_SYS_RAMBOOT
157 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
158 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
159 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
162 * Initial RAM Base Address Setup
164 #define CONFIG_SYS_INIT_RAM_LOCK 1
165 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
166 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
167 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
168 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
171 * Local Bus Configuration & Clock Setup
173 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
174 #define CONFIG_SYS_LBC_LBCR 0x00000000
177 * FLASH on the Local Bus
179 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
180 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
181 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
182 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
183 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
185 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
186 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
188 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
189 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
191 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
194 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
196 #undef CONFIG_SYS_FLASH_CHECKSUM
199 * SDRAM on the Local Bus
201 #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
203 #ifdef CONFIG_SYS_LB_SDRAM
204 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
205 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
207 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
208 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
210 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
212 * Base Register 2 and Option Register 2 configure SDRAM.
213 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
216 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
217 * port size = 32-bits = BR2[19:20] = 11
218 * no parity checking = BR2[21:22] = 00
219 * SDRAM for MSEL = BR2[24:26] = 011
222 * 0 4 8 12 16 20 24 28
223 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
225 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
226 * the top 17 bits of BR2.
229 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
232 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
235 * 64MB mask for AM, OR2[0:7] = 1111 1100
236 * XAM, OR2[17:18] = 11
237 * 9 columns OR2[19-21] = 010
238 * 13 rows OR2[23-25] = 100
239 * EAD set for extra time OR[31] = 1
241 * 0 4 8 12 16 20 24 28
242 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
245 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
247 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
248 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
250 #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
255 * Windows to access PIB via local bus
257 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
258 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
263 #define CONFIG_CONS_INDEX 1
264 #undef CONFIG_SERIAL_SOFTWARE_FIFO
265 #define CONFIG_SYS_NS16550
266 #define CONFIG_SYS_NS16550_SERIAL
267 #define CONFIG_SYS_NS16550_REG_SIZE 1
268 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
270 #define CONFIG_SYS_BAUDRATE_TABLE \
271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
276 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
277 /* Use the HUSH parser */
278 #define CONFIG_SYS_HUSH_PARSER
279 #ifdef CONFIG_SYS_HUSH_PARSER
280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
283 /* pass open firmware flat tree */
284 #define CONFIG_OF_LIBFDT 1
285 #define CONFIG_OF_BOARD_SETUP 1
286 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
289 #define CONFIG_HARD_I2C /* I2C with hardware support */
290 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
291 #define CONFIG_FSL_I2C
292 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
293 #define CONFIG_SYS_I2C_SLAVE 0x7F
294 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
295 #define CONFIG_SYS_I2C_OFFSET 0x3000
298 * Config on-board EEPROM
300 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
301 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
303 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
307 * Addresses are mapped 1-1.
309 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
310 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
311 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
312 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
313 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
314 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
315 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
316 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
317 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
320 #define CONFIG_PCI_SKIP_HOST_BRIDGE
321 #define CONFIG_NET_MULTI
322 #define CONFIG_PCI_PNP /* do pci plug-and-play */
324 #undef CONFIG_EEPRO100
325 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
326 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
328 #endif /* CONFIG_PCI */
331 #ifndef CONFIG_NET_MULTI
332 #define CONFIG_NET_MULTI 1
336 * QE UEC ethernet configuration
338 #define CONFIG_UEC_ETH
339 #define CONFIG_ETHPRIME "FSL UEC0"
341 #define CONFIG_UEC_ETH1 /* ETH3 */
343 #ifdef CONFIG_UEC_ETH1
344 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
345 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
346 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
347 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
348 #define CONFIG_SYS_UEC1_PHY_ADDR 4
349 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII
352 #define CONFIG_UEC_ETH2 /* ETH4 */
354 #ifdef CONFIG_UEC_ETH2
355 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
356 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
357 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
358 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
359 #define CONFIG_SYS_UEC2_PHY_ADDR 0
360 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII
366 #ifndef CONFIG_SYS_RAMBOOT
367 #define CONFIG_ENV_IS_IN_FLASH 1
368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
369 #define CONFIG_ENV_SECT_SIZE 0x20000
370 #define CONFIG_ENV_SIZE 0x2000
372 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
373 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
374 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
375 #define CONFIG_ENV_SIZE 0x2000
378 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
379 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
384 #define CONFIG_BOOTP_BOOTFILESIZE
385 #define CONFIG_BOOTP_BOOTPATH
386 #define CONFIG_BOOTP_GATEWAY
387 #define CONFIG_BOOTP_HOSTNAME
390 * Command line configuration.
392 #include <config_cmd_default.h>
394 #define CONFIG_CMD_PING
395 #define CONFIG_CMD_I2C
396 #define CONFIG_CMD_EEPROM
397 #define CONFIG_CMD_ASKENV
399 #if defined(CONFIG_PCI)
400 #define CONFIG_CMD_PCI
402 #if defined(CONFIG_SYS_RAMBOOT)
403 #undef CONFIG_CMD_SAVEENV
404 #undef CONFIG_CMD_LOADS
407 #undef CONFIG_WATCHDOG /* watchdog disabled */
410 * Miscellaneous configurable options
412 #define CONFIG_SYS_LONGHELP /* undef to save memory */
413 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
414 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
416 #if (CONFIG_CMD_KGDB)
417 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
419 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
422 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
423 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
424 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
425 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
428 * For booting Linux, the board info and command line data
429 * have to be in the first 8 MB of memory, since this is
430 * the maximum mapped by the Linux kernel during initialization.
432 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
437 #define CONFIG_SYS_HID0_INIT 0x000000000
438 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
439 #define CONFIG_SYS_HID2 HID2_HBE
444 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
446 /* DDR: cache cacheable */
447 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
448 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
449 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
450 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
452 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
453 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
454 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
455 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
456 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
457 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
459 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
460 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
461 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
462 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
463 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
464 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
466 #define CONFIG_SYS_IBAT3L (0)
467 #define CONFIG_SYS_IBAT3U (0)
468 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
469 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
471 /* Stack in dcache: cacheable, no memory coherence */
472 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
473 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
474 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
475 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
478 /* PCI MEM space: cacheable */
479 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
480 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
481 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
482 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
483 /* PCI MMIO space: cache-inhibit and guarded */
484 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
485 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
486 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
487 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
488 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
490 #define CONFIG_SYS_IBAT5L (0)
491 #define CONFIG_SYS_IBAT5U (0)
492 #define CONFIG_SYS_IBAT6L (0)
493 #define CONFIG_SYS_IBAT6U (0)
494 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
495 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
496 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
497 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
500 /* Nothing in BAT7 */
501 #define CONFIG_SYS_IBAT7L (0)
502 #define CONFIG_SYS_IBAT7U (0)
503 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
504 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
507 * Internal Definitions
511 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
512 #define BOOTFLAG_WARM 0x02 /* Software reboot */
514 #if (CONFIG_CMD_KGDB)
515 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
516 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
520 * Environment Configuration
522 #define CONFIG_ENV_OVERWRITE
524 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
525 #define CONFIG_ETHADDR 00:04:9f:ef:03:01
526 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
527 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
529 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
530 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
532 #define CONFIG_IPADDR 10.0.0.2
533 #define CONFIG_SERVERIP 10.0.0.1
534 #define CONFIG_GATEWAYIP 10.0.0.1
535 #define CONFIG_NETMASK 255.0.0.0
536 #define CONFIG_NETDEV eth1
538 #define CONFIG_HOSTNAME mpc8323erdb
539 #define CONFIG_ROOTPATH /nfsroot
540 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
541 #define CONFIG_BOOTFILE uImage
542 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
543 #define CONFIG_FDTFILE mpc832x_rdb.dtb
545 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
546 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
547 #define CONFIG_BAUDRATE 115200
549 #define XMK_STR(x) #x
550 #define MK_STR(x) XMK_STR(x)
552 #define CONFIG_EXTRA_ENV_SETTINGS \
553 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
554 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
555 "tftpflash=tftp $loadaddr $uboot;" \
556 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
557 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
558 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
559 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
560 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
562 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
563 "ramdiskaddr=1000000\0" \
564 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
566 "setbootargs=setenv bootargs " \
567 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
568 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
569 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
570 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
572 #define CONFIG_NFSBOOTCOMMAND \
573 "setenv rootdev /dev/nfs;" \
576 "tftp $loadaddr $bootfile;" \
577 "tftp $fdtaddr $fdtfile;" \
578 "bootm $loadaddr - $fdtaddr"
580 #define CONFIG_RAMBOOTCOMMAND \
581 "setenv rootdev /dev/ram;" \
583 "tftp $ramdiskaddr $ramdiskfile;" \
584 "tftp $loadaddr $bootfile;" \
585 "tftp $fdtaddr $fdtfile;" \
586 "bootm $loadaddr $ramdiskaddr $fdtaddr"
591 #endif /* __CONFIG_H */