2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
12 #define CONFIG_DISPLAY_BOARDINFO
15 * High Level Configuration Options
17 #define CONFIG_E300 1 /* E300 family */
18 #define CONFIG_QE 1 /* Has QE */
19 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
21 #define CONFIG_SYS_TEXT_BASE 0xFE000000
28 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
30 #ifndef CONFIG_SYS_CLK_FREQ
31 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
35 * Hardware Reset Configuration Word
37 #define CONFIG_SYS_HRCW_LOW (\
38 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39 HRCWL_DDR_TO_SCB_CLK_2X1 |\
41 HRCWL_CSB_TO_CLKIN_2X1 |\
42 HRCWL_CORE_TO_CSB_2_5X1 |\
43 HRCWL_CE_PLL_VCO_DIV_2 |\
44 HRCWL_CE_PLL_DIV_1X1 |\
47 #define CONFIG_SYS_HRCW_HIGH (\
49 HRCWH_PCI1_ARBITER_ENABLE |\
51 HRCWH_FROM_0X00000100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
61 #define CONFIG_SYS_SICRL 0x00000000
66 #define CONFIG_SYS_IMMR 0xE0000000
71 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
72 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
73 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
74 #define CONFIG_SYS_SPCR_OPT 1
79 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
83 #undef CONFIG_SPD_EEPROM
84 #if defined(CONFIG_SPD_EEPROM)
85 /* Determine DDR configuration from I2C interface
87 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
89 /* Manually set up DDR parameters
91 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
92 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
93 | CSCONFIG_ROW_BIT_13 \
96 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
97 | (0 << TIMING_CFG0_WRT_SHIFT) \
98 | (0 << TIMING_CFG0_RRT_SHIFT) \
99 | (0 << TIMING_CFG0_WWT_SHIFT) \
100 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
101 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
102 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
103 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
105 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
106 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
107 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
108 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
109 | (3 << TIMING_CFG1_REFREC_SHIFT) \
110 | (2 << TIMING_CFG1_WRREC_SHIFT) \
111 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
112 | (2 << TIMING_CFG1_WRTORD_SHIFT))
114 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
115 | (31 << TIMING_CFG2_CPO_SHIFT) \
116 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
117 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
118 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
119 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
120 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
123 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
125 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
126 | (0x0232 << SDRAM_MODE_SD_SHIFT))
128 #define CONFIG_SYS_DDR_MODE2 0x8000c000
129 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
130 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
133 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
134 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
137 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
143 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
144 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
145 #define CONFIG_SYS_MEMTEST_END 0x03f00000
148 * The reserved memory
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
153 #define CONFIG_SYS_RAMBOOT
155 #undef CONFIG_SYS_RAMBOOT
158 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
159 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
160 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
163 * Initial RAM Base Address Setup
165 #define CONFIG_SYS_INIT_RAM_LOCK 1
166 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
167 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
168 #define CONFIG_SYS_GBL_DATA_OFFSET \
169 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
172 * Local Bus Configuration & Clock Setup
174 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
175 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
176 #define CONFIG_SYS_LBC_LBCR 0x00000000
179 * FLASH on the Local Bus
181 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
182 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
183 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
184 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
185 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
187 /* Window base at flash base */
188 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
191 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
192 | BR_PS_16 /* 16 bit port */ \
193 | BR_MS_GPCM /* MSEL = GPCM */ \
195 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
206 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
207 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
209 #undef CONFIG_SYS_FLASH_CHECKSUM
214 #define CONFIG_CONS_INDEX 1
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE 1
217 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
219 #define CONFIG_SYS_BAUDRATE_TABLE \
220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
225 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
226 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
227 /* Use the HUSH parser */
228 #define CONFIG_SYS_HUSH_PARSER
230 /* pass open firmware flat tree */
231 #define CONFIG_OF_LIBFDT 1
232 #define CONFIG_OF_BOARD_SETUP 1
233 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
236 #define CONFIG_SYS_I2C
237 #define CONFIG_SYS_I2C_FSL
238 #define CONFIG_SYS_FSL_I2C_SPEED 400000
239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
241 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
244 * Config on-board EEPROM
246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
253 * Addresses are mapped 1-1.
255 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
256 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
257 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
258 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
259 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
260 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
261 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
262 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
263 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
266 #define CONFIG_PCI_INDIRECT_BRIDGE
267 #define CONFIG_PCI_SKIP_HOST_BRIDGE
268 #define CONFIG_PCI_PNP /* do pci plug-and-play */
270 #undef CONFIG_EEPRO100
271 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
272 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
274 #endif /* CONFIG_PCI */
277 * QE UEC ethernet configuration
279 #define CONFIG_UEC_ETH
280 #define CONFIG_ETHPRIME "UEC0"
282 #define CONFIG_UEC_ETH1 /* ETH3 */
284 #ifdef CONFIG_UEC_ETH1
285 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
286 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
287 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
288 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
289 #define CONFIG_SYS_UEC1_PHY_ADDR 4
290 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
291 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
294 #define CONFIG_UEC_ETH2 /* ETH4 */
296 #ifdef CONFIG_UEC_ETH2
297 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
298 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
299 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
300 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
301 #define CONFIG_SYS_UEC2_PHY_ADDR 0
302 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
303 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
309 #ifndef CONFIG_SYS_RAMBOOT
310 #define CONFIG_ENV_IS_IN_FLASH 1
311 #define CONFIG_ENV_ADDR \
312 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
313 #define CONFIG_ENV_SECT_SIZE 0x20000
314 #define CONFIG_ENV_SIZE 0x2000
316 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
317 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
318 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
319 #define CONFIG_ENV_SIZE 0x2000
322 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
323 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
328 #define CONFIG_BOOTP_BOOTFILESIZE
329 #define CONFIG_BOOTP_BOOTPATH
330 #define CONFIG_BOOTP_GATEWAY
331 #define CONFIG_BOOTP_HOSTNAME
334 * Command line configuration.
336 #define CONFIG_CMD_PING
337 #define CONFIG_CMD_I2C
338 #define CONFIG_CMD_EEPROM
339 #define CONFIG_CMD_ASKENV
341 #if defined(CONFIG_PCI)
342 #define CONFIG_CMD_PCI
345 #undef CONFIG_WATCHDOG /* watchdog disabled */
348 * Miscellaneous configurable options
350 #define CONFIG_SYS_LONGHELP /* undef to save memory */
351 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
353 #if (CONFIG_CMD_KGDB)
354 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
356 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
359 /* Print Buffer Size */
360 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
361 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
362 /* Boot Argument Buffer Size */
363 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
366 * For booting Linux, the board info and command line data
367 * have to be in the first 256 MB of memory, since this is
368 * the maximum mapped by the Linux kernel during initialization.
370 /* Initial Memory map for Linux */
371 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
376 #define CONFIG_SYS_HID0_INIT 0x000000000
377 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
378 HID0_ENABLE_INSTRUCTION_CACHE)
379 #define CONFIG_SYS_HID2 HID2_HBE
384 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
386 /* DDR: cache cacheable */
387 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
390 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
394 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
395 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
397 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
398 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
400 | BATL_CACHEINHIBIT \
401 | BATL_GUARDEDSTORAGE)
402 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
406 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
407 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
409 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
410 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
413 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
417 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
419 | BATL_CACHEINHIBIT \
420 | BATL_GUARDEDSTORAGE)
421 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
423 #define CONFIG_SYS_IBAT3L (0)
424 #define CONFIG_SYS_IBAT3U (0)
425 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
426 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
428 /* Stack in dcache: cacheable, no memory coherence */
429 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
430 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
434 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
435 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
438 /* PCI MEM space: cacheable */
439 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
442 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
446 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
447 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
448 /* PCI MMIO space: cache-inhibit and guarded */
449 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
451 | BATL_CACHEINHIBIT \
452 | BATL_GUARDEDSTORAGE)
453 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
457 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
458 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
460 #define CONFIG_SYS_IBAT5L (0)
461 #define CONFIG_SYS_IBAT5U (0)
462 #define CONFIG_SYS_IBAT6L (0)
463 #define CONFIG_SYS_IBAT6U (0)
464 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
465 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
466 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
467 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
470 /* Nothing in BAT7 */
471 #define CONFIG_SYS_IBAT7L (0)
472 #define CONFIG_SYS_IBAT7U (0)
473 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
474 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
476 #if (CONFIG_CMD_KGDB)
477 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
481 * Environment Configuration
483 #define CONFIG_ENV_OVERWRITE
485 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
486 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
488 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
489 * (see CONFIG_SYS_I2C_EEPROM) */
490 /* MAC address offset in I2C EEPROM */
491 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
493 #define CONFIG_NETDEV "eth1"
495 #define CONFIG_HOSTNAME mpc8323erdb
496 #define CONFIG_ROOTPATH "/nfsroot"
497 #define CONFIG_BOOTFILE "uImage"
498 /* U-Boot image on TFTP server */
499 #define CONFIG_UBOOTPATH "u-boot.bin"
500 #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
501 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
503 /* default location for tftp and bootm */
504 #define CONFIG_LOADADDR 800000
505 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
506 #define CONFIG_BAUDRATE 115200
508 #define CONFIG_EXTRA_ENV_SETTINGS \
509 "netdev=" CONFIG_NETDEV "\0" \
510 "uboot=" CONFIG_UBOOTPATH "\0" \
511 "tftpflash=tftp $loadaddr $uboot;" \
512 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
514 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
516 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
518 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
520 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
523 "fdtfile=" CONFIG_FDTFILE "\0" \
524 "ramdiskaddr=1000000\0" \
525 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
527 "setbootargs=setenv bootargs " \
528 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
529 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
530 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
532 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
534 #define CONFIG_NFSBOOTCOMMAND \
535 "setenv rootdev /dev/nfs;" \
538 "tftp $loadaddr $bootfile;" \
539 "tftp $fdtaddr $fdtfile;" \
540 "bootm $loadaddr - $fdtaddr"
542 #define CONFIG_RAMBOOTCOMMAND \
543 "setenv rootdev /dev/ram;" \
545 "tftp $ramdiskaddr $ramdiskfile;" \
546 "tftp $loadaddr $bootfile;" \
547 "tftp $fdtaddr $fdtfile;" \
548 "bootm $loadaddr $ramdiskaddr $fdtaddr"
550 #endif /* __CONFIG_H */