1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
11 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
12 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
14 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
22 * High Level Configuration Options
24 #define CONFIG_E300 1 /* E300 family */
25 #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
30 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
31 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
34 * Hardware Reset Configuration Word
35 * if CLKIN is 66.66MHz, then
36 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
38 #define CONFIG_SYS_HRCW_LOW (\
39 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 HRCWL_DDR_TO_SCB_CLK_2X1 |\
42 HRCWL_CSB_TO_CLKIN_2X1 |\
43 HRCWL_CORE_TO_CSB_3X1)
44 #define CONFIG_SYS_HRCW_HIGH_BASE (\
46 HRCWH_PCI1_ARBITER_ENABLE |\
48 HRCWH_BOOTSEQ_DISABLE |\
49 HRCWH_SW_WATCHDOG_DISABLE |\
50 HRCWH_TSEC1M_IN_RGMII |\
51 HRCWH_TSEC2M_IN_RGMII |\
55 #ifdef CONFIG_NAND_SPL
56 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
57 HRCWH_FROM_0XFFF00100 |\
58 HRCWH_ROM_LOC_NAND_SP_8BIT |\
61 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
62 HRCWH_FROM_0X00000100 |\
63 HRCWH_ROM_LOC_LOCAL_16BIT |\
70 #define CONFIG_SYS_SICRH 0x00000000
71 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
73 #define CONFIG_HWCONFIG
78 #define CONFIG_SYS_IMMR 0xE0000000
83 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
84 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
85 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
90 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
92 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
94 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
101 * Manually set up DDR parameters
102 * consist of two chips HY5PS12621BFP-C4 from HYNIX
104 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
105 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
106 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
107 | CSCONFIG_ODT_RD_NEVER \
108 | CSCONFIG_ODT_WR_ONLY_CURRENT \
109 | CSCONFIG_ROW_BIT_13 \
110 | CSCONFIG_COL_BIT_10)
112 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
113 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
114 | (0 << TIMING_CFG0_WRT_SHIFT) \
115 | (0 << TIMING_CFG0_RRT_SHIFT) \
116 | (0 << TIMING_CFG0_WWT_SHIFT) \
117 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
118 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
119 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
120 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
122 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
123 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
124 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
125 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
126 | (6 << TIMING_CFG1_REFREC_SHIFT) \
127 | (2 << TIMING_CFG1_WRREC_SHIFT) \
128 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
129 | (2 << TIMING_CFG1_WRTORD_SHIFT))
131 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
132 | (4 << TIMING_CFG2_CPO_SHIFT) \
133 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
134 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
135 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
136 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
137 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
139 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
140 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
142 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
143 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
146 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
147 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
148 | (0x0232 << SDRAM_MODE_SD_SHIFT))
149 /* ODT 150ohm CL=3, AL=1 on SDRAM */
150 #define CONFIG_SYS_DDR_MODE2 0x00000000
155 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
156 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
157 #define CONFIG_SYS_MEMTEST_END 0x00140000
160 * The reserved memory
162 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
163 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
166 * Initial RAM Base Address Setup
168 #define CONFIG_SYS_INIT_RAM_LOCK 1
169 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
171 #define CONFIG_SYS_GBL_DATA_OFFSET \
172 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175 * Local Bus Configuration & Clock Setup
177 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
178 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
179 #define CONFIG_SYS_LBC_LBCR 0x00040000
180 #define CONFIG_FSL_ELBC 1
183 * FLASH on the Local Bus
185 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
187 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
188 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
190 /* Window base at flash base */
191 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
192 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
194 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
195 /* 127 64KB sectors and 8 8KB top sectors per device */
196 #define CONFIG_SYS_MAX_FLASH_SECT 135
198 #undef CONFIG_SYS_FLASH_CHECKSUM
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
203 * NAND Flash on the Local Bus
206 #ifdef CONFIG_NAND_SPL
207 #define CONFIG_SYS_NAND_BASE 0xFFF00000
209 #define CONFIG_SYS_NAND_BASE 0xE0600000
212 #define CONFIG_MTD_PARTITION
214 #define CONFIG_SYS_MAX_NAND_DEVICE 1
215 #define CONFIG_NAND_FSL_ELBC 1
216 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
217 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
219 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
220 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
221 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
222 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
223 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
225 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
226 | BR_PS_16 /* 16 bit port */ \
227 | BR_MS_GPCM /* MSEL = GPCM */ \
229 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
238 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
239 | BR_DECC_CHK_GEN /* Use HW ECC */ \
240 | BR_PS_8 /* 8 bit port */ \
241 | BR_MS_FCM /* MSEL = FCM */ \
243 #define CONFIG_SYS_OR1_PRELIM \
253 /* Still needed for spl_minimal.c */
254 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
255 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
257 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
258 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
260 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
261 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
263 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
264 !defined(CONFIG_NAND_SPL)
265 #define CONFIG_SYS_RAMBOOT
267 #undef CONFIG_SYS_RAMBOOT
273 #define CONFIG_SYS_NS16550_SERIAL
274 #define CONFIG_SYS_NS16550_REG_SIZE 1
275 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
277 #define CONFIG_SYS_BAUDRATE_TABLE \
278 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
280 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
281 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
284 #define CONFIG_SYS_I2C
285 #define CONFIG_SYS_I2C_FSL
286 #define CONFIG_SYS_FSL_I2C_SPEED 400000
287 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
288 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
289 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
292 * Board info - revision and where boot from
294 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
297 * Config on-board RTC
299 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
300 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
304 * Addresses are mapped 1-1.
306 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
307 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
308 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
309 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
310 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
311 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
312 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
313 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
314 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
316 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
317 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
318 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
320 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
321 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
322 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
323 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
324 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
325 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
326 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
327 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
328 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
330 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
331 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
332 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
333 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
334 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
335 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
336 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
337 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
338 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
340 #define CONFIG_PCI_INDIRECT_BRIDGE
343 #define CONFIG_EEPRO100
344 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
345 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
347 #define CONFIG_HAS_FSL_DR_USB
348 #define CONFIG_SYS_SCCR_USBDRCM 3
350 #define CONFIG_USB_EHCI_FSL
351 #define CONFIG_USB_PHY_TYPE "utmi"
352 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
357 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
358 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
359 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
360 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
363 * TSEC ethernet configuration
365 #define CONFIG_TSEC1 1
366 #define CONFIG_TSEC1_NAME "eTSEC0"
367 #define CONFIG_TSEC2 1
368 #define CONFIG_TSEC2_NAME "eTSEC1"
369 #define TSEC1_PHY_ADDR 0
370 #define TSEC2_PHY_ADDR 1
371 #define TSEC1_PHYIDX 0
372 #define TSEC2_PHYIDX 0
373 #define TSEC1_FLAGS TSEC_GIGABIT
374 #define TSEC2_FLAGS TSEC_GIGABIT
376 /* Options are: eTSEC[0-1] */
377 #define CONFIG_ETHPRIME "eTSEC1"
382 #define CONFIG_SYS_SATA_MAX_DEVICE 2
384 #define CONFIG_SYS_SATA1_OFFSET 0x18000
385 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
386 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
388 #define CONFIG_SYS_SATA2_OFFSET 0x19000
389 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
390 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
392 #ifdef CONFIG_FSL_SATA
399 #if !defined(CONFIG_SYS_RAMBOOT)
400 #define CONFIG_ENV_ADDR \
401 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
402 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
403 #define CONFIG_ENV_SIZE 0x2000
405 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
406 #define CONFIG_ENV_SIZE 0x2000
409 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
410 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
415 #define CONFIG_BOOTP_BOOTFILESIZE
418 * Command line configuration.
421 #undef CONFIG_WATCHDOG /* watchdog disabled */
424 * Miscellaneous configurable options
426 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
429 * For booting Linux, the board info and command line data
430 * have to be in the first 256 MB of memory, since this is
431 * the maximum mapped by the Linux kernel during initialization.
433 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
434 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
439 #define CONFIG_SYS_HID0_INIT 0x000000000
440 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
441 HID0_ENABLE_INSTRUCTION_CACHE | \
442 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
443 #define CONFIG_SYS_HID2 HID2_HBE
448 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
450 /* DDR: cache cacheable */
451 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
454 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
458 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
459 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
461 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
462 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
464 | BATL_CACHEINHIBIT \
465 | BATL_GUARDEDSTORAGE)
466 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
470 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
471 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
473 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
474 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
477 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
481 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
483 | BATL_CACHEINHIBIT \
484 | BATL_GUARDEDSTORAGE)
485 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
487 /* Stack in dcache: cacheable, no memory coherence */
488 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
489 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
493 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
494 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
496 /* PCI MEM space: cacheable */
497 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
500 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
504 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
505 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
507 /* PCI MMIO space: cache-inhibit and guarded */
508 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
510 | BATL_CACHEINHIBIT \
511 | BATL_GUARDEDSTORAGE)
512 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
516 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
517 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
519 #define CONFIG_SYS_IBAT6L 0
520 #define CONFIG_SYS_IBAT6U 0
521 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
522 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
524 #define CONFIG_SYS_IBAT7L 0
525 #define CONFIG_SYS_IBAT7U 0
526 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
527 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
529 #if defined(CONFIG_CMD_KGDB)
530 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
534 * Environment Configuration
537 #define CONFIG_ENV_OVERWRITE
539 #if defined(CONFIG_TSEC_ENET)
540 #define CONFIG_HAS_ETH0
541 #define CONFIG_HAS_ETH1
544 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
546 #define CONFIG_EXTRA_ENV_SETTINGS \
548 "consoledev=ttyS0\0" \
549 "ramdiskaddr=1000000\0" \
550 "ramdiskfile=ramfs.83xx\0" \
552 "fdtfile=mpc8315erdb.dtb\0" \
553 "usb_phy_type=utmi\0" \
556 #define CONFIG_NFSBOOTCOMMAND \
557 "setenv bootargs root=/dev/nfs rw " \
558 "nfsroot=$serverip:$rootpath " \
559 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
561 "console=$consoledev,$baudrate $othbootargs;" \
562 "tftp $loadaddr $bootfile;" \
563 "tftp $fdtaddr $fdtfile;" \
564 "bootm $loadaddr - $fdtaddr"
566 #define CONFIG_RAMBOOTCOMMAND \
567 "setenv bootargs root=/dev/ram rw " \
568 "console=$consoledev,$baudrate $othbootargs;" \
569 "tftp $ramdiskaddr $ramdiskfile;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $fdtaddr $fdtfile;" \
572 "bootm $loadaddr $ramdiskaddr $fdtaddr"
574 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
576 #endif /* __CONFIG_H */